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M12L32321A-6BG 参数 Datasheet PDF下载

M12L32321A-6BG图片预览
型号: M12L32321A-6BG
PDF下载: 下载PDF文件 查看货源
内容描述: 512K X 32位X 2Banks同步DRAM [512K x 32Bit x 2Banks Synchronous DRAM]
分类和应用: 存储内存集成电路动态存储器
文件页数/大小: 28 页 / 649 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M12L32321A  
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)  
-5.5  
Max  
-6  
-7  
Parameter  
CAS Latency =3  
Symbol  
Unit  
Note  
Min  
5.5  
10  
-
Min  
6
Max  
Min  
Max  
7
10  
-
CLK cycle time  
tCC  
1000  
1000  
1000  
ns  
1
CAS Latency =2  
CAS Latency =3  
CAS Latency =2  
10  
-
6
6
6
6
6
6
CLK to valid  
output delay  
tSAC  
ns  
1
-
-
-
Output data hold time  
CLK high pulse width  
CLK low pulse width  
Input setup time  
tOH  
tCH  
tCL  
2.5  
ns  
ns  
ns  
ns  
ns  
ns  
2
3
3
3
3
2
2.5  
2
-
-
-
-
2.5  
2.5  
2.5  
2
-
-
2
2
2
2
0
-
2
-
-
-
tSS  
tSH  
tSLZ  
1.8  
1.2  
0
-
-
-
Input hold time  
-
-
2
-
CLK to output in Low-Z  
-
-
0
-
CAS Latency =3  
CAS Latency =2  
-
6
6
6
6
-
6
6
CLK to output in  
Hi-Z  
tSHZ  
-
ns  
-
-
-
*All AC parameters are measured from half to half.  
Note: 1.Parameters depend on programmed CAS latency.  
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.  
3.Assumed input rise and fall time (tr & tf)=1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the  
parameter.  
-5.5  
-6  
Symbol  
Parameter  
CAS Latency =3  
CAS Latency =2  
Unit  
ns  
Note  
Min  
Max  
5.5  
5.5  
-
Min  
Max  
5.5  
5.5  
-
-
-
-
-
CLK to valid  
output delay  
tSAC  
4
4
Output data hold time  
tOH  
2
ns  
2
-
CAS Latency =3  
CAS Latency =2  
5.5  
5.5  
-
-
5.5  
5.5  
CLK to output in  
Hi-Z  
tSHZ  
ns  
4
-
Note: 4. Special condition (Output Load 10 ohm+10 pF)  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Oct. 2008  
Revision : 1.1 6/28