ESMT
M12L32321A
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Clock
Generator
Bank B
Row
Address
Buffer
Address
&
Mode
Bank A
Refresh
Counter
Register
Sense Amplifier
Column
DQM0~3
CS
Address
Buffer
&
Column Decoder
RAS
CAS
WE
Refresh
Counter
Data Control Circuit
DQ
PIN FUNCTION DESCRIPTION
Pin
Name
System Clock
Input Function
Active on the positive going edge to sample all inputs.
CLK
CS
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
A0 ~ A10
BA
Address
Bank Select Address
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
Row Address Strobe
RAS
CAS
Column Address Strobe
CAS low.
Enables column access.
Enables write operation and row precharge.
Write Enable
WE
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM0~3
Data Input / Output Mask
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.1
2/28
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
