M11L416256A/M11L416256SA
TRUTH TABLE
ADDRESSES
FUNCTION
DQS
NOTES
RAS
CASL CASH
OE
WE
ROW
X
COL
X
Standby
H
L
L
L
L
H
X
H
X
X
H
H
H
L
X
L
L
L
X
High-Z
Read : Word
L
L
L
H
L
ROW
ROW
ROW
ROW
COL
COL
COL
COL
Data-Out
Read : Lower Byte
Read : Upper Byte
Write : Word (Early Write)
Lower Byte, Data-Out
Upper Byte, Data-Out
H
L
L
Data-In
Lower Byte, Data-In ,
Upper Byte, High-Z
Write : Lower Byte (Early)
Write : Upper Byte (Early)
L
L
L
H
L
L
X
X
ROW
ROW
COL
COL
Lower Byte, High-Z ,
Upper Byte, Data-In
H
L
L
L
Read-Write
1st Cycle
EDO-Page-Mode
2nd Cycle
Read
L
L
L
L
L
L
L
L
H
H
L L
H
ROW
ROW
COL
COL
COL
Data-Out, Data-In
Data-Out
1, 2
2
H
H
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
L
H
H
H
L
L
L
L
X
X
Data-Out
2
Any Cycle
Data-Out
2
1st Cycle
H
H
H
H
H
H
H
H
ROW
ROW
COL
COL
COL
COL
COL
Data-In
1
EDO-Page-Mode
Write
2nd Cycle
L
Data-In
1
1st Cycle
H
H
L L
L L
H
H
Data-Out, Data-In
Data-Out, Data-In
Data-Out
1, 2
1, 2
2
EDO-Page-Mode
Read-Write
2nd Cycle
Hidden Refresh
L
L
L
L
H
X
L
ROW
ROW
L
H
H
X
High-Z
RAS -Only Refresh
CBR Refresh
H
H
L
L
L
L
L
L
H
H
X
X
X
X
X
X
High-Z
High-Z
3
3
Self-Refresh
*Note : 1. These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active).
2. These READ cycles may also be BYTE READ cycles (either CASL or CASH active).
3. Only one CAS must be active ( CASL or CASH ).
Elite Memory Technology Inc
Publication Date: Agu. 2001
Revision : 1.3 7/16
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
