M11B1644A / M11B1644SA
M11L1644A / M11L1644SA
Notes :
1. Enables on-chip refresh and address counters.
cycle is READ-WRITE and the data output will contain
data read from the selected cell. If neither of the above
conditions is met, the state of I/O (at access time and
IH
IL
2. V (min) and V (max) are reference levels for
measuring timing of input signals. Transition times
IH
until CAS and RAS or OE go back to V ) is
IH
IL
are measured between V and V .
WE
indeterminate. OE held high and
taken low
3. In addition to meet the transition rate specification, all
after CAS goes low result in a LATE WRITE ( OE -
controlled) cycle.
IH
IL
input signals must transit between V and V in a
monotonic manner.
12. Those parameters are referenced to CAS leading
RCD
RCD
RCD
4. Assume that t
< t (max). If t
is greater than
WE
edge in EARLY WRITE cycles and
leading edge
the maximum recommended value shown in this
in LATE WRITE or READ-MODIFY- WRITE cycles.
RAC
RCD
table, t
will increase by the amount that t
13. During a READ cycle, if OE is low then taken HIGH
before CAS goes high, I/O goes open, if OE is tied
permanently low, a LATE WRITE or READ-MODIFY-
WRITE operation is not possible.
exceeds the value shown.
RCD
RCD
5. Assume that t
≥ t
(max)
6. If CAS is low at the falling edge of RAS , data-out
will be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS and
RAS must be pulsed high.
14. An initial pause of 200µ s is required after power-up
followed by eight RAS refresh cycles (RAS only or
CBR) before proper device operation is assured. The
eight RAS cycle wake-ups should be repeated any
REF
RCD
RCD
7. Operation within the t
limit ensures that t
(max)
RCD
can be met, t
point only ; if t
(max) is specified as a reference
time the t
refresh requirement is exceeded.
RCD
RCD
is greater than the specified t
WE
15. WRITE command is defined as
going low.
CAC
(max) limit, access time is controlled by t
.
16. LATE WRITE and READ-MODIFY-WRITE cycles must
RAD
RAD
8. Operation within the t
limit ensures that t (max)
OEH
have both tOFF2 and t
met ( OE high during
RAD
can be met. t (max) is specified as a reference
WRITE cycle) in order to ensure that the output buffers
will be open during the WRITE cycles.
RAD
RAD
point only ; if t
is greater than the specified t
AA
(max) limit, access time is controlled by t .
17. The I/Os open during READ cycles once tOFF1 or
tOFF2 occur.
RCH
RRH
9. Either t
or t
must be satisfied for a READ cycle.
OFF1
10.
t
(max) defines the time at which the output
18. Each CAS must meet minimum pulse width.
19. All IOs controlled by OE , regardless CAS .
achieves the open circuit condition ; it is not a
OH
OL
reference to V or V .
20. Self refresh mode is initiated by performing a CBR
refresh cycle and holding RAS low for the specified
tRASS. Self refresh mode is terminated by rising RAS
high for a minimum time of tRPS.
WCS
RWD
AWD
CWD
11.
t
, t
, t
and t
are restrictive operating
parameters in LATE WRITE and READ-MODIFY-
WRITE cycle only. If t
EARLY WRITE cycle and the data output will remain
WCS
WCS(min)
≥ t
, the cycle is an
RWD
an open circuit throughout the entire cycle. If t
21. For all of the refresh mode except the distributed CBR
refresh mode, all rows must be refreshed within the
refresh rate before and after self refresh.
RWD(min)
AWD
tAWD(min)
CWD
CWD(min)
≥ t
, t
≥
and t
≥ t
, the
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.1
6/16
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
