M11B1644A / M11B1644SA
M11L1644A / M11L1644SA
CC
CAPACITANCE (Ta = 25 , V = 5V ± 10% or 3.3V ± 10%)
°C
PARAMETER
Input Capacitance (address)
SYMBOL
TYP
MAX
5
UNIT
pF
I1
C
C
-
-
-
WE
Input Capacitance (RAS , CAS ,
Output capacitance (I/O0~I/O3)
, OE )
I2
7
pF
I / O
C
10
pF
CC
SS
AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70° , V =5V ± 10% or 3.3V ± 10%, V = 0V) (note 14)
C
Test Conditions
Input timing reference levels : 0.8V, 2.4V (for 5V power supply), 0.8V, 2.0V (for 3.3V power supply)
OL
OH
Output reference level : V = 0.8V, V =2.0V
Output Load : 2TTL gate + CL (50pF)
T
Assumed t = 2ns
-45
-50
-60
PARAMETER
SYMBOL
UNIT Notes
MIN
MAX
MIN
MAX
MIN
MAX
RC
Read or Write Cycle Time
Read Write Cycle Time
t
77
97
84
104
135
ns
ns
RWC
t
110
EDO-Page-Mode Read or Write Cycle
Time
PC
t
16
53
20
58
25
68
ns
ns
EDO-Page-Mode Read-Write Cycle
Time
PCM
t
RAC
CAC
t
t
t
45
11
50
13
60
15
ns
ns
4
5
Access Time From RAS
Access Time From CAS
OAC
AA
11
22
25
13
25
28
15
30
33
ns
ns
ns
13
Access Time From OE
Access Time From Column Address
t
ACP
t
Access Time From CAS Precharge
RAS Pulse Width
RAS
t
45
45
6
10,000
50
50
7
10,000
60
60
10
40
10
40
10
14
5
10,000
ns
RASC
RSH
t
100,000
100,000
100,000 ns
RAS Pulse Width (EDO Page Mode)
RAS Hold Time
t
ns
ns
RP
t
28
6
30
7
RAS Precharge Time
CAS Pulse Width
CAS
t
10,000
34
10,000
37
10,000
45
ns
ns
ns
ns
ns
18
CSH
CP
t
35
6
37
7
CAS Hold Time
t
6
7
CAS Precharge Time
RAS to CAS Delay Time
RCD
t
10
5
11
5
CRP
ASR
t
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
t
0
6
0
7
0
ns
ns
RAH
t
t
10
RAD
8
23
9
25
12
30
ns
8
RAS to Column Address Delay Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time (Reference
to RAS )
ASC
t
CAH
0
6
0
7
0
ns
ns
t
10
AR
t
40
23
10
44
25
11
55
30
13
ns
ns
ns
RAL
t
Column Address to RAS Lead Time
Column Address setup to CAS
precharge
ACH
t
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.1 4/16
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
