EFST
F49L040A
Read Mode
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain unchanged for over
250ns. The automatic sleep mode is independent of the
To read array data from the outputs, the system must
drive the
and
pins to VIL.
is the power
CE
OE
CE
control and selects the device.
is the output control
OE
and gates array data to the output pins.
should
WE
,
, and
control signals. Standard address
OE
WE
CE
remain at VIH. The internal state machine is set for
reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power
transition.
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC
Characteristics Table 8 represents the automatic sleep
mode current specification.
No command is necessary in this mode to obtain array
data. Standard microprocessor’s read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
Output Disable Mode
With the
is at a logic high level (V ), outputs from
IH
OE
the devices are disabled. This will cause the output pins
in a high impedance state
See “Read Command” section for more information.
Refer to the AC Read Operations Table 9 for timing
specifications and to Figure 5 for the timing diagram. ICC1
in the DC Characteristics Table 8 represents the active
current specification for reading array data.
Standby Mode
When
held at V
± 0.3V, the device enter
CE
CMOS Standby mode. If
CC
held at V , but not within
CE
IH
the range of V
± 0.3V, the device will still be in the
CC
Write Mode
standby mode, but the standby current will be larger.
To write a command or command sequence (which
includes programming data to the device and erasing
If the device is deselected during auto algorithm of
erasure or programming, the device draws active
sectors of memory), the system must drive
and
CE
WE
current I
until the operation is completed. I
in
CC2
CC3
to VIL, and
to VIH. The “Program Command” section
OE
the DC Characteristics Table 8 represents the standby
current specification.
has details on programming data to the device using
standard command sequences.
The device requires standard access time (t ) for
CE
An erase operation can erase one sector, multiple sectors,
or the entire device. Table 1 indicate the address space
that each sector occupies. A “sector address” consists of
the address bits required to uniquely select a sector. The
“Software Command Definitions” section has details on
erasing a sector or the entire chip, or suspending/resuming
the erase operation.
read access from either of these standby modes,
before it is ready to read data.
Sector Protect / Un-protect Mode
The hardware sector protect feature disables both
program and erase operations in any sector. The
hardware sector unprotect feature re-enables both the
program and erase operations in previously protected
sectors. Sector protect/unprotect can be implemented
A6 pin via programming equipment.
When the system writes the auto-select command
sequence, the device enters the auto-select mode. The
system can then read auto-select codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Auto-select Mode and Auto-select
Command sections for more information. ICC2 in the DC
Characteristics Table 8 represents the active current
specification for the write mode. The “AC Characteristics”
section contains timing specification Table 10 and timing
diagrams for write operations.
Elite Flash Storage Technology Inc.
Publication Date : Apr. 2005
Revision: 1.0
6/41
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
