EFST
F49L040A
Figure 16 shows the algorithms and Figure 15 shows
the timing diagram. This method uses standard
microprocessor bus cycle timing. For sector unprotect,
all unprotected sectors must first be protected prior to
the first sector unprotect write cycle.
When using programming equipment, this mode
requires V (11.5 V to 12.5 V) on address pin A9.
ID
While address pins A3, A2, A1, and A0 must be as
shown in Table 3.
To verify sector protection, all necessary pins have to
be set as required in Table 3, the programming
equipment may then read the corresponding identifier
code on DQ7-DQ0.
Auto-select Mode
The auto-select mode provides manufacturer and
device identification and sector protection verification,
through outputs on DQ7–DQ0. This mode is primarily
intended for programming equipment to automatically
To access the auto-select codes in-system, the host
system can issue the auto-select command via the
command register, as shown in Table 4. This method
match
a
device to be programmed with its
corresponding programming algorithm. However, the
auto-select codes can also be accessed in-system
through the command register.
does not require V . See “ Software Command
ID
Definitions” for details on using the auto-select mode.
7.2 Software Command Definitions
Writing specific address and data commands or
sequences into the command register initiates the
device operations. Table 4 defines the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper sequence
resets the device to reading array data.
All addresses are latched on the falling edge of
WE
or
, whichever happens later. All data is latched on
CE
the rising edge of
or
, whichever happens
WE
CE
first. Refer to the corresponding timing diagrams in
the AC Characteristics section.
Table 4. F49L040A Software Command Definitions
1st Bus 2nd Bus 3rd Bus 4th Bus
5th Bus
Cycle
6th Bus
Cycle
Bus
Cycle Cycle Cycle Cycle
Command
Cycles
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset (5)
Read (4)
1
1
4
6
6
XXXH F0H
RA RD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Program
555H AAH 2AAH 55H 555H A0H
PA
PD
Chip Erase
Sector Erase
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
SA
30H
Sector Erase
Suspend (6)
1
1
XXXH B0H
XXXH 30H
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Sector Erase Resume
(7)
-
-
-
Auto-select
See Table 5.
Notes:
1. X = don’t care
RA = Address of memory location to be read.
RD = Data to be read at location RA.
PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector.
2. Except Read command and Auto-select command, all command bus cycles are write operations.
3. Address bits A18–A16 are don’t cares.
4. No command cycles required when reading array data.
5. The system may read and program in non-erasing sectors, or enter the auto-select mode, when in the Erase
Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
6. The Erase Resume command is valid only during the Erase Suspend mode.
Elite Flash Storage Technology Inc.
Publication Date : Apr. 2005
Revision: 1.0 7/41
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
