EFST
4. PIN CONFIGURATIONS
4.1 32-pin TSOP I
F49L040A
OE
A10
CE
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
F49L040A
9
10
11
12
13
14
15
16
A1
A2
A3
A6
A5
A4
4.2 32-pin PLCC
4
3
2
1 32 31 30
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
5
A7
A6
A5
A4
A3
A2
A1
A0
6
7
8
9
10
11
12
13
DQ0
14 15 16 17 18 19 20
4.3 Pin Description
Symbol
A0~A18
Pin Name
Address Input
Functions
To provide memory addresses.
To output data when Read and receive data when Write.
The outputs are in tri-state when OE or CE is high.
DQ0~DQ7
Data Input/Output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
CE
OE
To activate the device when CE is low.
To gate the data output buffers.
To control the Write operations.
To provide power
WE
VCC
GND
Elite Flash Storage Technology Inc.
Publication Date : Apr. 2005
Revision: 1.0 2/41
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
