EFST
preliminary
F49L004UA / F49L004BA
4. PIN CONFIGURATIONS
4.1 40-pin TSOP I
A17
40
1
2
3
4
5
6
7
A16
A15
A14
A13
A12
A11
A9
VSS
39
N C
38
N C
37
A10
36
DQ7
35
DQ6
34
DQ5
8
A8
33
DQ4
32
9
WE
RESET
N C
RY/BY
A18
A7
VCC
10
11
12
13
14
15
16
17
18
19
20
31
VCC
30
N C
29
DQ3
28
DQ2
27
DQ1
26
A6
A5
A4
A3
A2
A1
DQ0
25
OE
24
VSS
23
CE
22
A0
21
4.2 32-pin PLCC
4
3
2
1 32 31 30
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
5
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
4.3 Pin Description
Symbol
A0~A18
Pin Name
Address Input
Functions
To provide memory addresses.
To output data when Read and receive data when Write.
The outputs are in tri-state when OE or CE is high.
To activate the device when CE is low.
To gate the data output buffers.
DQ0~DQ7
Data Input/Output
Chip Enable
Output Enable
Write Enable
Reset
CE
OE
To control the Write operations.
WE
Hardware Reset Pin/Sector Protect Unprotect (for 40-TSOP)
RESET
Ready/Busy
Power Supply
Ground
To check device operation status(for 40 TSOP)
To provide power
RY/BY
VCC
GND
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 2/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
