EFST
F49B002UA
Read Mode
Resetting the device
The reset command returns the device to Read mode.
This is a necessary step after reading the device or
manufacturer ID. Note: In these cases, if VID is
removed from the A9 pin, the device automatically
returns to Read mode and an explicit is not required.
To read array data from the outputs, the system must
drive the
and
pins to VIL.
is the power
CE
OE
CE
is the output control
control and selects the device.
OE
and gates array data to the output pins.
should
WE
remain at VIH. The internal state machine is set for
reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power
transition.
Boot block looking
To keep any system kernel code secure in the boot
block, the F49B002UA provides a command to lock
the boot block and prevent any accidental erasure or
reprogramming. The command sequence is similar to
the chip erase sequence except for the last cycle,
where 40H must be written into DQ0~DQ7 instead of
10H. The boot block is the only block that can be
locked in this way.
No command is necessary in this mode to obtain array
data. Standard microprocessor’s read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
Whether or not the boot block has been locked can be
detected by the command sequence shown in Table 4.
This command sequence returns a “1” on DQ0 if the
boot block is locked; a “0” if the boot block has not
been locked and it is open to erasing and
programming.
See “Read Command” section for more information.
Refer to the AC Read Operations Table 9 for timing
specifications and to Figure 5 for the timing diagram. ICC1
in the DC Characteristics Table 8 represents the active
current specification for reading array data.
Write Mode
Output Disable Mode
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive
With the
is at a logic high level (V ), outputs from
IH
OE
and
CE
WE
the devices are disabled. This will cause the output pins
in a high impedance state
to VIL, and
to VIH. The “Program Command” section
OE
has details on programming data to the device using
standard command sequences.
Standby Mode
An erase operation can erase one sector, or the entire
device. Table 1 indicate the address space that each
sector occupies. A “sector address” consists of the address
bits required to uniquely select a sector. The “Software
Command Definitions” section has details on erasing a
sector or the entire chip.
When
held at V
± 0.3V, the device enter
CE
CC
CE
± 0.3V, the device will still be in the
CMOS Standby mode. If
held at V , but not within
IH
the range of V
CC
standby mode, but the standby current will be larger.
When the system writes the auto-select command
sequence, the device enters the auto-select mode. The
system can then read auto-select codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Auto-select Mode and Auto-select
Command sections for more information. ICC2 in the DC
Characteristics Table 8 represents the active current
specification for the write mode. The “AC Characteristics”
section contains timing specification Table 10 and timing
diagrams for write operations.
If the device is deselected during auto algorithm of
erasure or programming, the device draws active
current I
until the operation is completed. I
in
CC3
CC2
the DC Characteristics Table 8 represents the standby
current specification.
The device requires standard access time (t ) for
CE
read access from either of these standby modes,
before it is ready to read data.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
5/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
