EFST
F49B002UA
Read Command
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase.
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation
immediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
the data integrity.
See the “Read Mode” in the “Read Operations” section
for more information. Refer to AC Read Operation Table
9. & Figure 5 for the timing diagram.
Program Command
The program command sequence programs one byte
into the device. Programming is a four-bus-cycle
operation. The program command sequence is initiated
by writing two unlock write cycles, followed by the
program set-up command. The program address and
data are written next, which in turn initiate the
Embedded Program algorithm. The system is not
required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verifies the programmed cell
margin.
The system can determine the status of the erase
operation by using DQ7 or DQ6, See “Programming &
Erasing Operation Status” section for more information
on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. See the Erase/Program
Operations Table 10,11 in “AC Characteristics” for
parameters.
Sector Erase Command
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7 and DQ6. See “Write Operation Status” section for
more information on these status bits.
Sector erase is a six-bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command.
Any commands written to the device during the
Embedded Program Algorithm are ignored. The
Program command sequence should be reinitiated once
the device has reset to reading array data, to ensure
data integrity.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase
algorithm automatically programs and verifies the
sector for an all zero data pattern prior to electrical
erase. The system is not required to provide any
controls or timings during these operations.
Programming is allowed in any sequence and across
sector boundaries. A bit can’t be programmed from a “0”
back to a “1”. Attempting to do so may halt the operation
or cause the Data Polling algorithm to indicate the
operation was successful. However, a succeeding read
will show that the data is still “0”. Only erase operations
can convert a “0” to a “1”.
The Sector Erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure the data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6
(Refer to “Programming & Erasing Operation Status”
section for more information on these status bits.)
Refer to the Erase/Program Operations Table 10,11 in
the “AC Characteristics” section for parameters.
Chip Erase Command
Chip erase is a six-bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
8/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
