EFST
F49B002UA
4. PIN CONFIGURATIONS
4.1 32-pin PDIP
VDD
WE
A17
A14
A13
A8
1
2
3
4
5
6
7
8
N C
A16
A15
A12
A7
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
A6
A9
A5
A11
OE
A4
32-Pin
DIP
A3
9
A10
CE
A2
10
11
12
13
14
15
16
A1
DQ7
DQ6
DQ5
DQ4
DQ3
A0
DQ0
DQ1
DQ2
GND
4.2 32-pin PLCC
4
3
2
1 32 31 30
A14
A13
A8
2 9
5
6
7
8
9
10
11
12
13
A7
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
A6
A5
A9
A4
A11
OE
A3
A2
A10
CE
A1
A0
DQ7
DQ0
14 15 16 17 18 19 20
4.3 Pin Description
Symbol
A0~A17
Pin Name
Functions
To provide memory addresses.
Address Input
To output data when Read and receive data when Write.
DQ0~DQ7
Data Input/Output
The outputs are in tri-state when OE or CE is high.
Chip Enable
Output Enable
Write Enable
CE
OE
To activate the device when CE is low.
To gate the data output buffers.
To control the Write operations.
WE
NC
VCC
No connection
Power Supply
Ground
Unconnected pin
To provide power
GND
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4 2/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
