ESMT
F25L08QA (2S)
PIN DESCRIPTION
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing for serial input and output operations
To transfer commands, addresses or data serially into the device. Data is
latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO
pin to transfer commands, addresses or data serially into the device on the
rising edge of SCK and read data or status from the device on the falling edge
of SCK(for Dual/Quad mode).
Serial Data Input /
Serial Data Input Output 0
SI / SIO0
To transfer data serially out of the device. Data is shifted out on the falling edge
of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands,
addresses or data serially into the device on the rising edge of SCK and read
data or status from the device on the falling edge of SCK (for Dual/Quad
mode).
Serial Data Output /
Serial Data Input Output 1
SO / SIO1
Chip Enable
CE
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status
register. / Bidirectional IO pin to transfer commands, addresses or data serially
into the device on the rising edge of SCK and read data or status from the
device on the falling edge of SCK (for Quad mode).
Write Protect /
Serial Data Input Output 2
WP / SIO2
To temporality stop serial communication with SPI flash memory without
resetting the device. / Bidirectional IO pin to transfer commands, addresses or
data serially into the device on the rising edge of SCK and read data or status
from the device on the falling edge of SCK (for Quad mode).
Hold /
HOLD / SIO3
Serial Data Input Output 3
VDD
VSS
Power Supply
Ground
To provide power.
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
4/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
