ESMT
F25L08QA (2S)
STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Default at
Power-up
Bit
Name
Function
Read/Write
Status Register -1
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
1
BUSY
WEL
0
0
R
R
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
2
3
4
5
BP0
BP1
BP2
BP3
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
0
0
0
0
R/W
R/W
R/W
R/W
1 = Quad enabled
0 = Quad disabled
6
7
QE
0
0
R/W
R/W
1 = BP3, BP2,BP1,BP0 are read-only bits
0 = BP3, BP2,BP1,BP0 are read/writable
BPL
Default at
Power-up
Bit
Name
Function
Read/Write
Status Register -2
8
SUS
Suspend Status
0
0
R
9~15
Reserved
Reserved for future use
N/A
Note:
1. BUSY and WEL are read only.
2. BP0~3, QE and BPL bits are non-volatile.
Write Enable Latch (WEL)
BUSY
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
The BUSY bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the BUSY bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
• Power-up
• Write Disable (WRDI) instruction completion
• Page Program instruction completion
• Sector Erase instruction completion
• Block Erase instruction completion
• Chip Erase instruction completion
• Write Status Register instructions
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
8/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
