EN25F40A
Figure 2. BLOCK DIAGRAM
Flash
Memory
X-Decoder
Address
Buffer
And
Latches
Y-Decoder
I/O Buffers
and
Control Logic
Data Latches
Serial Interface
CS#
CLK
DI (DQ0)
DO (DQ1) WP# (DQ2)
HOLD# (DQ3)
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ0 ~ DQ3 are used for Quad instructions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Elite Semiconductor Memory Technology Inc.
3
Rev. D, Issue Date: 2017/02/13