EN25F40A
Figure.1 CONNECTION DIAGRAMS
CS#
VCC
1
2
3
4
8
7
6
5
DO (DQ1)
WP# (DQ2)
VSS
HOLD# (DQ3)
CLK
DI (DQ0)
8 - LEAD SOP / VSOP
CS#
DO (DQ1)
WP# (DQ2)
VSS
VCC
1
2
3
4
8
7
6
5
HOLD# (DQ3)
CLK
DI (DQ0)
8 - LEAD USON / VDFN
Table 1. Pin Names
Symbol
CLK
Pin Name
Serial Clock Input
*1
DI (DQ0)
DO (DQ1)
CS#
Serial Data Input (Data Input Output 0)
Serial Data Output (Data Input Output 1)
Chip Select
*1
*2
WP# (DQ2)
HOLD# (DQ3)
Vcc
Write Protect (Data Input Output 2)
*2
HOLD# pin (Data Input Output 3)
Supply Voltage (2.7-3.6V)
Ground
Vss
No Connect
NC
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ2 ~ DQ3 are used for Quad instructions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Elite Semiconductor Memory Technology Inc.
2
Rev. D, Issue Date: 2017/02/13
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
