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EN5337QI-E 参数 Datasheet PDF下载

EN5337QI-E图片预览
型号: EN5337QI-E
PDF下载: 下载PDF文件 查看货源
内容描述: 3A电压模式同步降压PWM DC -DC转换器集成电感器 [3A Voltage Mode Synchronous Buck PWM DC-DC Converter with Integrated Inductor]
分类和应用: 转换器电感器
文件页数/大小: 12 页 / 271 K
品牌: ENPIRION [ ENPIRION, INC. ]
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EN5337QI  
Electrical Characteristics  
NOTE: VIN=5.5V over operating temperature range unless otherwise noted. Typical values are at TA = 25°C.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
Operating Input Voltage  
VIN  
2.375  
5.5  
V
Under Voltage Lock-out –  
VIN Rising  
Voltage above which UVLO is not  
asserted  
VUVLOR  
VUVLOF  
2.2  
V
Under Voltage Lock-out –  
VIN Falling  
Voltage below which UVLO is  
asserted  
2.1  
100  
0.75  
V
μA  
V
Shut-Down Supply Current IS  
ENABLE=0V  
Feedback node voltage – factory  
setting – TA = 25°C  
Feedback Pin Voltage  
VXFB  
0.735  
-5  
0.765  
5
Feedback pin Input  
Leakage Current 1  
IXFB  
XFB pin input leakage current  
nA  
Line Regulation  
2.375V VIN 5.5V  
0A ILOAD 3A  
0.02  
-0.03  
0.003  
%/V  
%/A  
ΔVOUT_LINE  
ΔVOUT_LOAD  
Load Regulation  
Temperature Regulation  
ΔVOUT_TEMP -40°C TEMP 85°C  
Measured from when VIN VUVLOR  
ENABLE pin voltage crosses logic  
%/°C  
&
CSS X  
67 kΩ  
VOUT Rise Time  
tRISE  
high threshold. (4.7nF CSS 100nF)  
Rise Time Accuracy 1  
4.7nF CSS 100nF  
-25  
3
+25  
%
ΔTRISE  
Output Drop Out  
Voltage  
mV  
VDO  
RDO  
VINMIN - VOUT at Full load  
Input to Output Resistance  
250  
83  
500  
167  
Resistance 1  
mΩ  
Maximum Continuous  
Output Current  
IOUT_Max_Cont  
A
Over Current Trip Level  
Disable Threshold  
IOCP  
4.5  
A
V
VDISABLE  
ENABLE pin logic low.  
0.0  
1.8  
0.8  
VIN  
ENABLE pin logic high  
2.375V VIN 5.5V  
ENABLE Threshold  
VENABLE  
V
Time for device to re-enable after a  
falling edge on ENABLE pin  
ENABLE Lock-out time  
TENLO  
700  
5
µS  
μA  
ENABLE pin Input Current1 IENABLE  
70  
ENABLE pin has ~80kΩ pull down  
Switching Frequency (Free  
Running)  
Free Running frequency of  
oscillator  
FSW  
MHz  
External SYNC Clock  
Frequency Lock Range  
FPLL_LOCK  
Range of SYNC clock frequency  
SYNC Clock Logic Level  
4.5  
1.8  
5.5  
0.8  
2.5  
MHz  
V
SYNC Input Threshold –  
Low  
VSYNC_LO  
SYNC Input Threshold –  
High  
VSYNC_HI  
POKTH  
SYNC Clock Logic Level  
V
Output voltage as a fraction of expected  
output voltage  
POK Threshold  
90  
%
POK Output Low Voltage  
POK Output Hi Voltage  
VPOKL  
VPOKH  
With 4mA current sink into POK  
0.4  
VIN  
V
V
2.375V VIN 5.5V  
POK pin VOH Leakage  
Current1  
IPOKL  
POK high  
1
µA  
Note 1: Parameter guaranteed by design  
©Enpirion 2009 all rights reserved, E&OE  
4
www.enpirion.com  
02638  
6/18/2009  
Rev:D