EN5337QI
Rise Time: TR ≈ (Css* 67kΩ) ± 25%
• Power good circuit indicating the output
voltage is between 90% and 120% of
programmed value as long as the feedback
loop is closed.
During start-up of the converter, the reference
voltage to the error amplifier is linearly
increased to its final level by an internal current
source of approximately 10uA. The soft start
capacitor should be between 4.7nF and 100nf.
Typical soft-start rise time is ~1mS with SS
capacitor value of 15nF. The rise time is
measured from when VIN ≥ VUVLOR and
ENABLE pin voltage crosses its logic high
threshold to when VOUT reaches its
programmed value.
Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device.
Applying logic high will enable the converter
into normal operation. When the ENABLE pin
is asserted (high) the device will undergo a
normal soft start. A logic low will disable the
converter. A logic low will power down the
device in a controlled manner and the device is
POK Operation
subsequently shut down.
The device will
remain shut-down for the duration of the
ENABLE lockout time (see Electrical
Characteristics Table). If the ENABLE signal is
re-asserted during this time, the device will
power up with a normal soft-start at the end of
the ENABLE lockout time.
The POK signal is an open drain signal
(requires a pull up resistor to VIN or similar
voltage) from the converter indicating the
output voltage is within the specified range.
The POK signal will be logic high (VIN) when
the output voltage is above 90% of
programmed VOUT. If the output voltage goes
below this threshold, the POK signal will be at
logic low.
Frequency Synchronization
The switching frequency of the DC/DC
converter can be phase-locked to an external
clock source to move unwanted beat
frequencies out of band. To avail this feature,
the clock source should be connected to the
SYNC pin. An activity detector recognizes the
presence of an external clock signal and
automatically phase-locks the internal oscillator
to this external clock. Phase-lock will occur as
long as the input clock frequency is in the
range of 4.5 to 5.5 MHz. When no clock signal
is present, the device reverts to the free
running frequency of the internal oscillator.
Over-Current Protection
The current limit function is achieved by
sensing the current flowing through the Power
PFET. When the sensed current exceeds the
over current trip point, both power FETs are
turned off for the remainder of the switching
cycle. If the over-current condition is removed,
the over-current protection circuit will enable
normal PWM operation. If the over-current
condition persists, the soft start capacitor will
gradually discharge causing the output voltage
to fall. When the OCP fault is removed, the
output voltage will ramp back up to the desired
voltage. This circuit is designed to provide high
noise immunity.
Spread Spectrum Mode
The external clock frequency may be swept
between 4.5 MHz and 5.5 MHz at repetition
rates of up to 10 kHz in order to reduce EMI
frequency components.
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the Junction temperature
exceeds approximately 150ºC. After a thermal
Soft-Start Operation
Soft start is a means to reduce the in-rush
current when the device is enabled. The output
voltage is ramped up gradually upon start-up.
The output rise time is controlled by the choice
of soft-start capacitor, which is placed between
the SS pin (pin 30) and the AGND pin (pin 32).
shutdown
event,
when
the
junction
temperature drops by approx 20ºC, the
converter will re-start with a normal soft-start.
©Enpirion 2009 all rights reserved, E&OE
8
www.enpirion.com
02638
6/18/2009
Rev:D
ENPIRION [ ENPIRION, INC. ]
