EM198810 Datasheet
INTEGRATED CIRCUIT
Elan Design
4 Digital Base Band Interface
4.1 SPI Command Format
The SPI interface is used to program the IC via the 4 pins SPI_CLK, SPI_SS, SPI_MOSI and
SPI_MISO. The SPI_MOSI and SPI_CLK pins are used to load data into an internal shift register. The
SPI_MOSI and SPI_CLK pins are use to send data to microcontroller. The data are loaded into the
shift register and sent to microcontroller on the rising edge of the clock SPI_CLK and latched on the
rising edge of the SPI_SS signal. When the SPI_SS pin is high, the data stored in the shift register is
retained even if a SPI_CLK is applied. When the SPI_SS pin is low the data can be rewritten and
resent. Inputs timing of the SPI_CLK, SPI_SS, SPI_MOSI and SPI_MISOD are shown in the Fig.2.
Format 1
CKPHA = 0:
SPI_CLK
SPI_SS
SPI_MOSI R/W A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SPI_MISO
S7 S6 S5 S4 S3 S2 S1 S0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Format 2
CKPHA = 1:
SPI_CLK
SPI_SS
D15
D6
SPI_MOSI
SPI_MISO
R/W A6 A5 A4 A3 A2 A1 A0
D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7
D5 D4 D3 D2 D1 D0
S7 S6 S5 S4 S3 S2 S1 S0
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
- Fig. 3 –
4.2 Register Information
4.2.1 Package type define and FIFO point set
preamble SYNC trailer
payload
CRC
Automatically set FIFO write_point=0
when RX received SYNC
Automatically set FIFO read_point=0
when RX received SYNC or after transmit SYNC when TX
- Figure 4 –
* Preamble: 1 ~ 8 bytes programmable
* SYNC: 32/48/64 bits programmable as device syncword
* Trailer: 4~16 bits programmable
* Payload: TX/RX data, there are 4 data types: raw data, 8_10 bits, Manchester, interleave
with FEC option
* CRC: 16 bit CRC is option
Note: For transmit, it is needed to clear FIFO write point before application write in data via access reg82[15].
This spec is subject to change
without any notice
9 / 18
24.Dec.2006
ELAN [ ELAN MICROELECTRONICS CORP ]
