EM198810 Datasheet
INTEGRATED CIRCUIT
Elan Design
3. Pins names and pins location
3.1 Pins names
SYMBOL
Type
PIN
DESCRIPTION
Power supply voltage.
VDD
VDD
NC
GND
ANT
VDD
NC
PWR
PWR
--
GND
50ΩRF
PWR
--
1
2
3
4
5
DO NOT CONNECT. Reserved for factory test.
Ground connection.
RF input/output.
Power supply voltage.
DO NOT CONNECT. Reserved for factory test.
6
7
NC
--
8
9
Power supply voltage.
VDD
VDD
NC
NC
NC
PWR
PWR
--
--
--
10
11
12
13
14
DO NOT CONNECT. Reserved for factory test.
Outputs 1MHz TX symbol clock, 12MHz APLL, or crystal clock.
See register definitions for details.
BRCLK
O
Transmit/Receive packet process flag.
PKT_FLAG
RXCLK
O
O
15
16
Receiver symbol timing clock recovery output.
Fixed at 1MHz fundamental rate.
FIFO full/empty flag.
Power supply voltage.
Ground connection.
Enable line for the SPI bus. Active low.
Data input for the SPI bus.
Clock line for the SPI bus.
When RESET_n is low, most of the chip shuts down to conserve
power.
FIFO_FLAG
VDD
GND
SPI_SS
SPI_MOSI
SPI_CLK
RESET_n
O
PWR
GND
17
18
19
20
21
22
23
I
I
I
I
When raised high, RESET_n is used to turn on the chip,restoring all
registers to their default value.
Data output for the SPI bus.
SPI_MISO
VDD_IO
LDO_VDD
LDO_OUT
LOD_TUNE
GND
VDD
XTALO
XTALI
O
24
25
26
27
28
29
30
31
Vdd for the digital i/o pins. Nominally +3.3 VDC.
Unregulated input to the on-chip LDO volt. regulator.
+1.8V output of the on-chip LDO voltage regulator.
Fine-tune for the on-chip LDO voltage regulator.
Ground connection.
PWR
PWR
PWR
--
GND
PWR
AO
Power supply voltage.
Output of the crystal oscillator gain block.
Input to the crystal oscillator gain block.
Ground connection.
AI
GND
32
Exposed
pad
GND
- Table 1 –
This spec is subject to change
without any notice
6 / 18
24.Dec.2006
ELAN [ ELAN MICROELECTRONICS CORP ]
