EBJ20UF8BCF0
Pin Description
Pin name
Function
Address input
Row address
Column address
A0 to A14
A0 to A14
A0 to A9
A10 (AP)
Auto precharge
A12 (/BC)
Burst chop
BA0, BA1, BA2
Bank select address
Row address strobe
/RAS
/CAS
Column address strobe
Write enable
/WE
/CS0
Chip select
CKE0
Clock enable
CK0
Clock input
/CK0
Differential clock input
ODT control
ODT0
DQ0 to DQ63
Data input/output
DQS0 to DQS7, /DQS0 to /DQS7
Input and output data strobe
Input mask
DM0 to DM7
SCL
Clock input for serial PD
Data input/output for serial PD
Address input for serial PD
Power for internal circuit
Power for serial PD
Reference voltage for CA
Reference voltage for DQ
Ground
SDA
SA0, SA1, SA2
VDD*1
VDDSPD
VREFCA
VREFDQ
VSS
VTT
I/O termination supply for SDRAM
Set DRAM to a known state
No connection
/RESET
NC
Note: 1. The VDD and VDDQ pins are tied common to a single power-plane on these designs.
Front side
1 pin
48 pin49 pin
120 pin
240 pin
121 pin
168 pin 169 pin
Back side
Data Sheet E1689E21 (Ver. 2.1)
4
ELPIDA [ ELPIDA MEMORY ]
