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E1922E20 参数 Datasheet PDF下载

E1922E20图片预览
型号: E1922E20
PDF下载: 下载PDF文件 查看货源
内容描述: 4G位DDR3L SDRAM [4G bits DDR3L SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 29 页 / 426 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG  
1.3 Recommended DC Operating Conditions  
Table 3: Recommended DC Operating Conditions (TC = 0°C to +85°C), DDR3L Operation  
Parameter  
Symbol  
VDD  
min.  
typ.  
1.35  
1.35  
max.  
1.45  
1.45  
Unit  
V
Notes  
Supply voltage  
Supply voltage for DQ  
1.283  
1.283  
1, 2, 3, 4  
1, 2, 3, 4  
VDDQ  
V
Notes: 1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very  
long period of time (e.g. 1 sec).  
2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.  
3. Under these supply voltages, the device operates to this DDR3L specifcation.  
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while  
5. VDD and VDDQ are changed for DDR3 operation shown as following timing wave form.  
Table 4: Recommended DC Operating Conditions (TC = 0°C to +85°C), DDR3 Operation  
Parameter  
Symbol  
VDD  
min  
typ  
1.5  
1.5  
max  
Unit  
V
Notes  
1, 2, 3  
1, 2, 3  
Supply voltage  
Supply voltage for DQ  
1.425  
1.425  
1.575  
1.575  
VDDQ  
V
Notes: 1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.  
2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifcations under the same speedtimings as defined  
for this device.  
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ  
are changed for DDR3L operation shown as below.  
Ta  
Tb  
Tc  
Td  
Te  
Tf  
Tg  
Th  
Ti  
Tj  
Tk  
CK, /CK  
tCKSRX  
T(min) = 10ns  
VDD, VDDQ (DDR3)  
VDD, VDDQ (DDR3L)  
T(min) = 10ns  
T(min) = 200μs  
T = 500μs  
/RESET  
CKE  
tIS  
T(min) = 10ns  
Valid  
tDLLK  
ZQCL  
tXPR  
tMRD  
tMRD  
tMRD  
tMOD  
tZQinit  
*1  
tIS  
*1  
MRS  
MR2  
MRS  
MR3  
MRS  
MR1  
MRS  
MR0  
Valid  
Valid  
Command  
BA  
ODT  
RTT  
tIS  
tIS  
Valid  
Static low in case RTT_Nore is enabled at time Tg, otherwise static high or low  
: VIH or VIL  
Note: 1. From time point Td until Tk, NOP or DES commands must be applied between MRS and ZQCL commands.  
Figure 1: VDD/VDDQ Voltage Switch between DDR3L and DDR3  
Data Sheet E1922E20 (Ver. 2.0)  
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