EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG
Pin Configurations
Pin Configurations (×4/×8 configuration)
/xxx indicates active low signal.
78-ball FBGA (×4 configuration)
78-ball FBGA (×8 configuration)
1
2
3
7
8
9
1
2
3
7
8
9
A
B
A
B
VSS
VDD
NC
NC
VSS
VDD
VSS
VDD
NC
NU/(/TDQS) VSS
VDD
VSS VSSQ DQ0
DM VSSQ VDDQ
VSS VSSQ DQ0
VDDQ
DM/TDQS VSSQ VDDQ
C
D
C
D
VDDQ
VSSQ
DQ2 DQS
NC /DQS
DQ1
VDD
NC
DQ3 VSSQ
VSSQ
NC VDDQ
NC
VDD CKE
DQ2 DQS
DQ1
VDD
DQ7
DQ3 VSSQ
VSSQ
VSS
VSSQ DQ6 /DQS
VSS
DQ5
E
F
G
H
J
E
F
G
H
J
DQ4
VREFDQ VDDQ NC
NC VSS /RAS
ODT VDD /CAS
VREFDQ VDDQ
VDDQ
NC
CK
/CK
VSS
NC
VSS /RAS
CK
/CK
VSS
ODT VDD /CAS
VDD CKE
A10(AP)
A10(AP)
ZQ
NC
ZQ
NC
NC
/CS
BA0
A3
/WE
BA2
A0
NC
/CS
/WE
VSS
VDD
VSS
VDD
VSS
VSS
VDD
BA0
A3
BA2
A0
A15 VREFCA VSS
A15 VREFCA VSS
K
L
K
L
A12(/BC) BA1
VDD
VSS
VDD
VSS
A12(/BC) BA1
VDD
VSS
VDD
VSS
A5
A2
A1
A4
A6
A8
VSS
VDD
VSS
A5
A7
A2
A9
A1
A4
A6
A8
M
N
M
N
A7
A9
A11
A14
A11
A14
/RESET A13
/RESET A13
(Top view)
(Top view)
Pin name
Function
Pin name
Function
Address inputs
A0 to A15*3
A10(AP): Auto precharge
A12(/BC): Burst chop
/RESET*3
Active low asynchronous reset
BA0 to BA2*3
DQ0 to DQ7
DQS, /DQS
TDQS, /TDQS
/CS*3
Bank select
VDD
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Data input/output
Differential data strobe
Termination data strobe
Chip select
VSS
VDDQ
VSSQ
VREFDQ
VREFCA
ZQ
NC*1
NU*2
Reference voltage for DQ
Reference voltage for CA
Reference pin for ZQ calibration
No connection
/RAS, /CAS, /WE*3
CKE*3
Command input
Clock enable
CK, /CK
Differential clock input
Write data mask
ODT control
DM
ODT*3
Not usable
Notes: 1. Not internally connected with die.
2. Don't connect. Internally connected.
3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1922E20 (Ver. 2.0)
3
ELPIDA [ ELPIDA MEMORY ]
