+/+…when timing is critical
C9824
Low EMI Clock Generator for Intel 133MHz/3 DIMM Chipset Systems
Preliminary
Power on Bi-Directional Pins
Power Up Condition:
Pin 4 is a Power up bi-directional pin and is used for selecting the host frequency in page 1, table 1. During power-up of
the device, this pin is in input mode (see Fig 4, below), therefore; it is considered input select pin, Sel1 internal to the IC.
After a settling time, the selection data is latched into the internal control register and then this pin becomes a clock
output.
VDD Rail
Power Supply
Ramp
REF / FSEL1
(Pin 4)
-
Hi-Z Inputs
Toggle Outputs
Select data is latched into register, then the pin becomes a REF clock output signal.
Fig.4
Vdd
Strapping Resistor Options:
R up
The power up bi-directional pin has a large value pull-
down (50KΩ+/−25KΩ), therefore, a selection “0” is the
default. If the system uses a slow power supply (over
10mS settling time), then it is recommended to use an
external Pull-down (Rdn) in order to insure a low
selection. In this case, the designer may choose one of
two configurations, see Fig.5A and 5B.
1K
IM I C 9824
Bidirectional
JP1
JU MPER
R d
Load
R dn
5K
Fig. 5A represents an additional pull down resistor 5KΩ
connected from the pin to ground, which allows a faster
pulldown to a high level.
Fig. 5A
If a selection “1” is desired, then a jumper is placed on
JP1 to connect the pin to a 1 KΩ resistor as shown in
Fig.5A. Please note the selection resistors (Rup and
Rdn) are placed before the Damping resistor (Rd) and
close to the pin.
JP2
3 W ay Jum per
Vdd
3
2
1
R sel
5K
IM I C 9824
Fig. 5B represent a single resistor 5KΩ connected to a
3-way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
R d
Load
Bidirectional
Fig. 5B
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.0
2/15/2000
Page 6 of 17
CYPRESS [ CYPRESS ]
