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C9824AY 参数 Datasheet PDF下载

C9824AY图片预览
型号: C9824AY
PDF下载: 下载PDF文件 查看货源
内容描述: [Processor Specific Clock Generator, CMOS, PDSO56, SSOP-56]
分类和应用: 光电二极管外围集成电路
文件页数/大小: 17 页 / 327 K
品牌: CYPRESS [ CYPRESS ]
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+/+…when timing is critical  
C9824  
Low EMI Clock Generator for Intel 133MHz/3 DIMM Chipset Systems  
Preliminary  
2-Wire I2C Control Interface  
The 2-wire control interface implements a read/write slave only interface in accordance with the Philips I²C specification.  
(See Fig. 6 below). The device can be read back by using standard I2C command bytes. Sub addressing is not  
supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control  
interface allows each clock output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer  
is supported.  
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is  
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the  
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer  
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer  
cycle is an 8-bit address. The LSB address Byte = 0 in write mode.  
The device will respond to transfers of 10 bytes (max) of data at the I2C address D2. The device will generate an  
acknowledge (low) signal on the SDATA wire following reception of each byte. Data is transferred MSB first at a max  
rate of 100kbits/S. This device will also respond to a D3 address which sets it in a read mode. It will not respond to any  
other control interface conditions, and previously set control registers are retained.  
Transmit  
ACK  
ACK  
ACK  
ACK  
ACK  
Receive  
COMMAND BYTE  
(Don't Care)  
BYTE COUNT  
(Don't Care)  
BYTE 0  
(Valid)  
BYTE N  
(Valid)  
1
1
0
1
0
0
1
0
SDATA  
MSB  
LSB  
8
8
8
8
SCLK  
START CONDITION  
STOP CONDITION  
Fig.6a (WRITE)  
Transmit  
ACK BYTE COUNT  
BYTE 0  
(Valid)  
BYTE1  
(Valid)  
BYTE N  
(Valid)  
Receiv  
ACK  
ACK  
ACK  
ACK  
1
1
0
1
0
1
0
1
(Valid)  
SDATA  
MSB  
LSB  
8
8
8
8
SCLK  
START CONDITION  
STOP CONDITION  
Fig.6b (READ)  
Figure 6  
I2C Communications Waveforms  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,  
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571  
http://www.imicorp.com  
Rev 1.0  
2/15/2000  
Page 7 of 17