+/+…when timing is critical
C9824
Low EMI Clock Generator for Intel 133MHz/3 DIMM Chipset Systems
Preliminary
Pin Description
PIN No.
Pin Name
I/O
Description
4
I/O This pin is a bidirectional pin. During its input time it serves as a select straps for CPU
clock frequency. This pin contains a 50K device internal pulldown (+/-20K) resistor. See
Frequency Select Table (p. 1) for REF/FSEL1 strap functionality. After the initial input
time it becomes a 3.3v 14.318 MHz clock output.
REF/SEL1
6
7
I
On-chip reference oscillator input pin. Requires either an external parallel resonant
crystal (nominally 14.318 MHz) or externally generated reference signal
On-chip reference oscillator pin. Drives an external parallel resonant crystal. When an
externally generated reference signal is used at Xin, this pin remains unconnected.
3.3V Fixed 66 MHz clock outputs.
XIN
O
XOUT
10,11, 12
15, 16
26, 27
28
O
O
O
I
3V66(0:2)
PCI(0:1)
48M(1:2)
TS#
3.3V Fixed 33.3 Mhz PCI clock outputs.
3.3V Fixed 48 MHz clock outputs. Used for DOT and USB clocks.
3.3V LVTTL compatible inputs for tri-state control. If TS# = 0, then all outputs are in Hi-Z
state.
21
I
3.3V LVTTL compatible input. When held LOW, the device enters a power down mode.
See description page 3. This pin has a device Internal Pull-Up resistor. Typical 250KΩ
(range 200KΩ to 500KΩ)
PD#
18
I
3.3 LVTTL compatible inputs for logic selection. See Frequency Select Table (p. 1) for
SEL0 functionality.
SEL0
29,32, 33, 36,
37, 38, 41,
42, 45, 46,
47, 50 51,
53, 54
1
23
O
3.3V SDRAM DIMM clocks. See table1, p.1 for frequency selection. See fig.3, page 4 for
timing relationship.
SDRAM(0:12)
O
O
2.5V Host clock outputs. See table 1 p. 1 for frequency selection.
2.5V IOAPIC clock outputs. See fig.3 p.4 for timing relationship.
CPU (0:1)
IOAPIC
SDATA
SCLK
I/O I2C compatible SDATA
22
I
I2C compatible SCLK
5, 9, 14, 25
20
19
3.3V Common Power Supply
Analog circuitry 3.3V Power Supply
Analog circuitry power supply Ground pins.
2.5V Power Supply’s
VDD
VDDA
VSSA
VDDC, VDDI
VSS
2, 56
3, 8, 13, 17,
24, 30, 34,
39, 43, 48,
52, 55
3.3 V Power supply ground pins.
49, 44, 40,
35, 31
3.3V power support for SDRAM clock output drivers.
VDDS
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.0
2/15/2000
Page 2 of 17
CYPRESS [ CYPRESS ]
