+/+…when timing is critical
C9810
Low EMI Clock Generator for Intel 810 Chipset for Mobile Applications
Advanced Information
IMI Confidential
Test Mode Function
Test Mode Functionality
SEL2 SEL1
SEL0
CPU
SDRAM
3V66
PCI
48 MHz
REF
TCLK
IOAPIC
x
0
1
TCLK÷2
TCLK÷2
TCLK÷3
Table 2
TCLK÷6
TCLK÷2
TCLK÷6
Note: TCLK is a test clock over driven on the XIN input during test mode.
Power Management Functions
Power Management on this device is controlled by a single pin, PD# (pin32). When PD# is high (default) the device is in
running and all signals are active.
When PD# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies (3.3V and
2.5V except for VDDA/pin 27) may be removed. When in power down, all outputs are synchronously stopped in a low
state (see Fig.2 below), all PLL’s are shut off, and the crystal oscillator is disabled. When the device is shutdown the I²C
function is also disabled.
Power Management Timing
0nS
100MHz
10nS
20nS
30nS
40nS
50nS
CPU
3V66
66MHz
33MHz
33MHz
PCI
IOAPIC
PWRDN#
Undefined
Undefined
Undefined
SDRAM 100MHz
14.3MHz
48MHz
REF
USB
Fig.2
Power Management Current
Maximum 2.5 Volt Current
Consumption (VDD2.5 =2.625)
Maximum 3.3 Volt Current Consumption
(VDD3.3 = 3.465 V)
PD#, SEL[2..0]
(CPU Clock)
0XXX (Power down)
1010 (66MHz)
100 µA
70 mA
100 mA
200 µA
280 mA
280 mA
280 mA
1011 (100MHz)
111X (133MHz)
133 mA
Table 3
When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200mS before
releasing the PD# pin high.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Rev 0.4
8/31/1999
Page 3 of 15
http://www.imicorp.com
CYPRESS [ CYPRESS ]
