B9940L
2.5V / 3.3V, 200 MHz, 1:18 Clock Distribution Buffer
AC Parameters1
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
Fmax
Tpd
Maximum Input Frequency
PECL_CLK to Q Delay2,4
200
4.0
5.2
3.8
4.4
55
MHz
ns
2.0
2.6
1.8
2.3
45
3.5
4.0
3.3
3.8
VDD = 3.3V
VDD = 2.5V
Tpd
TTL_CLK to Q Delay2,4
ns
VDD=3.3V
VDD = 2.5V
FoutDC
Tskew
Output Duty Cycle2,3,4
Output-to-Output Skew2,4
%
Measured at VDDC/2
VDD=3.3V, Fin = 150MHz
VDD=2.5V, Fin = 150MHz
PECL, VDDC = 3.3V
PECL, VDDC = 2.5V
TCLK, VDDC = 3.3V
TCLK, VDDC = 2.5V
PECL_CLK
150
200
1.4
2.2
1.2
1.7
850
750
1.1
ps
Tskew(pp)
Tskew(pp)
Tskew(pp)
Tr / Tf
Part-to-Part Skew5
Part-to-Part Skew5
ns
ns
ps
ns
Part to Part Skew6
TCLK
Output Clocks Rise / Fall Time2,4
0.3
0.3
0.7V to 2.0V,
VDDC = 3.3V
1.2
0.5V to 1.8V,
VDDC = 2.5V
VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = -40°C to +85°C
Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with
loaded outputs.
Note 2: Outputs driving 50Ω transmission lines.
Note 3: 50% input duty cycle.
Note 4: Outputs loaded with 30pF each
Note 5: Across temperature and voltage ranges, includes output skew
Note 6: For a specific temperature and voltage, includes output skew
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07105 Rev. **
5/24/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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