B9940L
2.5V / 3.3V, 200 MHz, 1:18 Clock Distribution Buffer
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
-65°C to + 150°C
-40°C to +85°C
2kV
Maximum Power Supply:
Maximum Input Current:
5.5V
±20mA
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
Characteristic
Symbol Min
Typ
Max
0.8
Units
Conditions
Input Low Voltage
Input High Voltage
VIL
VSS
2.0
All other inputs
VIH
VDD
V
All other inputs
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Peak-to-Peak Input Voltage
PECL_CLK
IIL1
IIH1
VPP
-200
200
µA
µA
500
1000
mV
Common Mode Range
PECL_CLK
VCMR2
VDD-
1.4
-
-
VDD-
0.6
V
VDD = 3.3V
VDD = 2.5V
VDD-
1.0
VDD-
0.6
Output Low Voltage
Output High Voltage
VOL3
VOH3
0.5
V
V
IOL = 20mA
2.4
1.8
-
IOH = -20mA, VDDC = 3.3V
IOH = -20mA, VDDC = 2.5V
Quiescent Supply Current
Output Impedance
IDD
Zout
Cin
2
23
4
5
28
-
mA
Ω
18
Input Capacitance
-
pF
VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = -40°C to +85°C
Note 1: Inputs have pull-up/pull-down resistors that effect input current.
Note 2: The VCMR is the difference from the most positive side of the differential input signal. Normal operation is
obtained when the “High” input is within the VCMR range and the input lies within the VPP specification.
Note 3: Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07105 Rev. **
5/24/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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