B9940L
2.5V / 3.3V, 200 MHz, 1:18 Clock Distribution Buffer
Pin Description
PIN
NAME
PECL_CLK
PECL_CLK#
TCLK
PWR
I/O
I, PU
I, PD
I, PD
O
Description
5
6
3
PECL Input Clock.
PECL Input Clock.
External Reference/Test Clock Input.
Clock Outputs.
9, 10, 11, 13, 14,
15, 18, 19, 20,
22, 23, 24, 26,
27, 28, 30, 31,
32
VDDC
Q(17:0)
Clock Select Input. When low, PECL clock is selected and when high
TCLK is selected.
4
I, PD
TCLK_SEL
8, 16, 29
7, 21
1, 2, 12, 17, 25
3.3V or 2.5V Power Supply for Output Clock Buffers.
3.3V or 2.5V Power Supply
Common Ground
VDDC
VDD
VSS
PD = Internal Pull-Down, PU = Internal Pull-Up.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07105 Rev. **
5/24/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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