P R E L I M I N A R Y
Figure 35. Read Address Skew ..................................................... 61
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 59
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 59
pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 60
pSRAM Power on and Deep Power Down . . . . . 60
Figure 33. Deep Power-down Timing.............................................. 60
Figure 34. Power-on Timing............................................................ 60
pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 61
Figure 36. Write Address Skew...................................................... 61
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 62
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm .............62
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 63
4
Am49DL32xBG
July 19, 2002
CYPRESS [ CYPRESS ]
