P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . .10
Flash Device Bus Operations . . . . . . . . . . . . . . . 12
Word/Byte Configuration ........................................................12
Requirements for Reading Array Data ...................................12
Writing Commands/Command Sequences ............................12
Accelerated Program Operation ..........................................12
Autoselect Functions ...........................................................12
Simultaneous Read/Write Operations with Zero Latency .......12
Standby Mode ........................................................................ 13
Automatic Sleep Mode ...........................................................13
RESET#: Hardware Reset Pin ...............................................13
Output Disable Mode .............................................................. 13
Table 3. Device Bank Division ........................................................13
Table 4. Top Boot Sector Addresses .............................................14
Table 6. Bottom Boot Sector Addresses .........................................16
Autoselect Mode ..................................................................... 18
Sector/Sector Block Protection and Unprotection ..................18
Table 8. Top Boot Sector/Sector Block Addresses
Write Operation Status . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data# Polling .................................................................32
Figure 5. Data# Polling Algorithm .................................................. 32
RY/BY#: Ready/Busy# ............................................................ 33
DQ6: Toggle Bit I ....................................................................33
Figure 6. Toggle Bit Algorithm........................................................ 33
DQ2: Toggle Bit II ................................................................... 34
Reading Toggle Bits DQ6/DQ2 ...............................................34
DQ5: Exceeded Timing Limits ................................................ 34
DQ3: Sector Erase Timer ....................................................... 34
Table 18. Write Operation Status ................................................... 35
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 36
Industrial (I) Devices ............................................................ 36
V f/V s Supply Voltage ...................................................36
CC CC
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 37
CMOS Compatible ..................................................................37
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents)............................................................. 39
Figure 10. Typical ICC1 vs. Frequency............................................ 39
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Test Setup.................................................................... 40
Figure 12. Input Waveforms and Measurement Levels ................. 40
pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 41
CE#s Timing ...........................................................................41
Figure 13. Timing Diagram for Alternating
for Protection/Unprotection .............................................................18
Table 9. Bottom Boot Sector/Sector Block Addresses
Between Pseudo SRAM to Flash................................................... 41
Read-Only Operations ...........................................................42
Figure 14. Read Operation Timings ............................................... 42
Hardware Reset (RESET#) .................................................... 43
Figure 15. Reset Timings ............................................................... 43
Word/Byte Configuration (CIOf) ..............................................44
Figure 16. CIOf Timings for Read Operations................................ 44
Figure 17. CIOf Timings for Write Operations................................ 44
Erase and Program Operations ..............................................45
Figure 18. Program Operation Timings.......................................... 46
Figure 19. Accelerated Program Timing Diagram.......................... 46
Figure 20. Chip/Sector Erase Operation Timings .......................... 47
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 48
Figure 22. Data# Polling Timings (During Embedded Algorithms). 48
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 49
Figure 24. DQ2 vs. DQ6................................................................. 49
Temporary Sector Unprotect .................................................. 50
Figure 25. Temporary Sector Unprotect Timing Diagram .............. 50
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 51
Alternate CE#f Controlled Erase and Program Operations ....52
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 53
Read Cycle .............................................................................54
Figure 28. Psuedo SRAM Read Cycle........................................... 54
Figure 29. Page Read Timing ........................................................ 55
Write Cycle .............................................................................56
Figure 30. Pseudo SRAM Write Cycle—WE# Control................... 56
Figure 31. Pseudo SRAM Write Cycle—CE1#s Control................ 57
Figure 32. Pseudo SRAM Write Cycle—
for Protection/Unprotection .............................................................19
Write Protect (WP#) ................................................................19
Temporary Sector/Sector Block Unprotect ............................. 19
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algo-
rithms .............................................................................................. 21
SecSi (Secured Silicon) Sector Flash Memory Region .......... 22
Factory Locked: SecSi Sector Programmed and Protected At
the Factory .......................................................................... 22
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ...........................................................22
Hardware Data Protection ......................................................22
Low VCC Write Inhibit ...........................................................22
Write Pulse “Glitch” Protection ............................................22
Logical Inhibit ......................................................................22
Power-Up Write Inhibit .........................................................23
Common Flash Memory Interface (CFI) . . . . . . .23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
Reading Array Data ................................................................26
Reset Command .....................................................................26
Autoselect Command Sequence ............................................26
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..26
Byte/Word Program Command Sequence ............................. 27
Unlock Bypass Command Sequence .................................. 27
Figure 3. Program Operation .......................................................... 28
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................28
Erase Suspend/Erase Resume Commands ........................... 29
Figure 4. Erase Operation............................................................... 29
Table 15. Autoselect Device IDs (Word Mode) ...............................30
Table 17. Autoselect Device IDs (Byte Mode) ................................31
UB#s and LB#s Control.................................................................. 58
Flash Erase And Programming Performance . . 59
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 59
July 19, 2002
Am49DL32xBG
3
CYPRESS [ CYPRESS ]
