CY7C4282V
CY7C4292V
Switching Waveforms
Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
17
t
ENH
t
ENS
WEN
FF
NO OPERATION
t
t
WFF
WFF
[10]
t
SKEW1
RCLK
REN
4282V–6
Read Cycle Timing
t
CLK
t
t
CLKL
CLKH
RCLK
t
t
ENH
ENS
REN
EF
NO OPERATION
t
REF
t
REF
t
A
VALID DATA
Q
–Q
17
0
t
OLZ
t
OHZ
t
OE
OE
[11]
t
SKEW1
WCLK
WEN
4282V–7
Notes:
10.
t
SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
SKEW1 is also the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
11.
t
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
6
CYPRESS [ CYPRESS ]
