CY7C4282V
CY7C4292V
Switching Waveforms (continued)
[12]
Reset Timing
t
RSS
[13]
LD
t
RS
RS
t
RSR
REN,WEN
t
RSF
RSF
RSF
EF,PAE
FF,PAF
t
t
[14]
OE=1
–
Q
Q
8
0
OE=0
4282V–8
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D –D
0
D
0
D
1
D
2
D
3
D
4
(FIRSTVALIDWRITE)
8
t
ENS
[15]
FRL
t
WEN
t
SKEW1
RCLK
t
REF
EF
REN
–Q
[16]
t
A
t
A
Q
D
0
D
1
0
8
t
OLZ
t
OE
OE
4282V–9
Notes:
12. The clocks (RCLK, WCLK) can be free-running during reset.
13. For standalone or width expansion configuration only.
14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
15. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1
.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
16. The first word is available the cycle after EF goes HIGH, always.
7
CYPRESS [ CYPRESS ]
