CY7C4282V
CY7C4292V
Pin Configuration
STQFP
Top View
48
47
1
2
Q5
Q4
GND
Q3
Q2
VCC
Q1
Q0
GND
N/C
FF
EF
OE
GND
FL/RT
N/C
WEN
RS
D8
D7
D6
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D5
46
45
3
4
44
43
42
5
6
7
CY7C4282V
CY7C4292V
41
40
39
8
9
10
38
37
36
11
12
13
14
15
35
34
D4
D3
D2
33
16
4282V–2
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle
Functional Description (continued)
The CY7C4282V/92V provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to sin-
gle word granularity. The programmable flags default to Emp-
ty+7 and Full−7.
All configurations are fabricated using an advanced 0.35µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
Selection Guide
7C4282V/92V-10
7C4282V/92V-15
7C4282V/92V-25
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
100
8
66.7
10
15
4
40
15
25
6
10
3.5
0
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
0
1
8
10
25
30
15
25
Active Power Supply
Commercial
Industrial
25
Current (I ) (mA)
CC
CY7C4282V
64k x 9
CY7C4292V
128k x 9
64-pin 10x10 TQFP
Density
Package
64-pin 10x10 TQFP
2
CYPRESS [ CYPRESS ]
