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5962-9759802QYA 参数 Datasheet PDF下载

5962-9759802QYA图片预览
型号: 5962-9759802QYA
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 19ns, 128-Cell, CMOS, CQCC84, CERAMIC, LCC-84]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 17 页 / 640 K
品牌: CYPRESS [ CYPRESS ]
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CY7C375i  
Switching Characteristics Over the Operating Range[13]  
7C375i83  
7C375i66  
7C375i125 7C375i100 7C374iL83 7C375iL66  
Parameter  
Combinatorial Mode Parameters  
tPD  
Input to Combinatorial Output[1]  
Description  
Min. Max. Min. Max. Min. Max. Min. Max. Unit  
10  
13  
12  
15  
15  
18  
20  
22  
ns  
ns  
tPDL  
Input to Output Through Transparent Input  
or Output Latch[1]  
tPDLL  
Input to Output Through Transparent Input  
and Output Latches[1]  
15  
16  
19  
24  
ns  
tEA  
tER  
Input to Output Enable[1]  
14  
14  
16  
16  
19  
19  
24  
24  
ns  
ns  
Input to Output Disable  
Input Registered/Latched Mode Parameters  
tWL  
tWH  
tIS  
Clock or Latch Enable Input LOW Time[9]  
Clock or Latch Enable Input HIGH Time[9]  
Input Register or Latch Set-Up Time  
Input Register or Latch Hold Time  
3
3
2
2
3
3
2
2
4
4
3
3
5
5
4
4
ns  
ns  
ns  
ns  
ns  
tIH  
tICO  
Input Register Clock or Latch Enable to  
Combinatorial Output[1]  
14  
16  
16  
18  
19  
21  
24  
26  
tICOL  
Input Register Clock or Latch Enable to  
Output Through Transparent Output  
Latch[1]  
ns  
Ouptut Registered/Latched Mode Parameters  
tCO  
tS  
Clock or Latch Enable to Output[1]  
6.5  
14  
7
8
10  
24  
ns  
ns  
Set-Up Time from Input to Clock or Latch  
Enable  
5.5  
0
6
0
8
0
10  
0
tH  
Register or Latch Data Hold Time  
ns  
ns  
tCO2  
Output Clock or Latch Enable to Output  
Delay (Through Memory Array)[1]  
16  
19  
tSCS  
Output Clock or Latch Enable to Output  
Clock or Latch Enable (Through Memory  
Array)  
8
10  
0
10  
12  
0
12  
15  
0
15  
20  
0
ns  
ns  
ns  
tSL  
Set-Up Time from Input Through Transpar-  
ent Latch to Output Register Clock or Latch  
Enable  
tHL  
Hold Time for Input Through Transparent  
Latch from Output Register Clock or Latch  
Enable  
fMAX1  
fMAX2  
Maximum Frequency with Internal Feed-  
125  
100  
143  
83  
66  
MHz  
MHz  
[9]  
back (Least of 1/tSCS, 1/(tS + tH), or 1/tCO  
)
Maximum Frequency Data Path in Output 158.3  
Registered/LatchedMode(Lesserof1/(tWL  
125  
100  
+ tWH), 1/(tS + tH), or 1/tCO  
Maximum Frequency with External Feed-  
back (Lesser of 1/(tCO + tS) and 1/(tWL  
tWH  
)
fMAX3  
83.3  
0
76.9  
0
62.5  
0
50  
0
MHz  
ns  
+
,
tOHtIH  
37x  
Output Data Stable from Output Clock  
Minus Input Register Hold Time for  
7C37x[9, 14]  
Notes:  
13. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.  
14. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C375i. This specification is met  
for the devices operating at the same ambient temperature and at the same power supply voltage.  
Document #: 38-03029 Rev. **  
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