CY7C375i
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the FLASH370i PLDs. Note that product term allocation is han-
dled by software and is invisible to the user.
compatible with 5.0V systems. When VCCIO pins are connect-
ed to a 3.3V source, the input voltage levels are compatible
with both 5.0V and 3.3V systems, while the output voltage lev-
els are compatible with 3.3V systems. There will be an addi-
tional timing delay on all output buffers when operating in 3.3V
I/O mode. The added flexibility of 3.3V I/O capability is avail-
able in commercial and industrial temperature ranges.
I/O Macrocell
Each of the macrocells on the CY7C375i has a separate I/O
pin associated with it. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term alloca-
tor. The macrocell includes a register that can be optionally
bypassed, polarity control over the input sum-term, and four
global clocks to trigger the register. The macrocell also fea-
tures a separate feedback path to the PIM so that the register
can be buried if the I/O pin is used as an input.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus re-
ducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to VCC or GND.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C375i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Design Tools
Programming
Development software for the CY7C375i is available from Cy-
press’s Warp™, Warp Professional™, and Warp Enterprise™
software packages. Please refer to the data sheets on these
products for more details. Cypress also actively supports al-
most all third-party design tools. Please refer to third-party tool
support for further information.
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An In-
troduction to In System Reprogramming with FLASH370i.”
Maximum Ratings
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
3.3V or 5.0V I/O operation
The FLASH370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of VCC pins:
one set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V source, the I/O voltage levels are
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage .................................................... 12.5V
Output Current into Outputs ........................................ 16 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Ambient
Temperature
VCC
VCCINT
Range
VCCIO
Commercial
0°C to +70°C
−40°C to +85°C
–55°C to +125°C
5V ± 0.25V
5V ± 0.5V
5V ± 0.5V
5V ± 0.25V
OR
3.3V ± 0.3V
Industrial
5V ± 0.5V
OR
3.3V ± 0.3V
Military[2]
Note:
2. TA is the “instant on” case temperature.
Document #: 38-03029 Rev. **
Page 5 of 17
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