STK12C68
HARDWARE MODE SELECTION
E
H
L
W
X
H
L
HSB
A
- A (hex)
0
MODE
Not Selected
I/O
POWER
NOTES
12
H
X
X
X
X
Output High Z
Output Data
Input Data
Standby
Active
Active
l
H
Read SRAM
o
L
H
Write SRAM
X
X
L
Nonvolatile STORE
Output High Z
m
CC
2
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l
L
L
H
H
H
H
n, o
n, o
Nonvolatile STORE
CC
2
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
Nonvolatile RECALL
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,
the part will go into standby mode, inhibiting all operations until HSB rises.
Note n: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note o: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
e
HARDWARE STORE CYCLE
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK12C68
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
1
MAX
22
23
24
25
26
t
t
t
t
t
t
t
t
STORE Cycle Duration
10
ms
μs
ns
ns
ns
i, p
i, q
p, r
STORE
DELAY
RECOVER
HLHX
HLHZ
HLQZ
HHQX
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
700
300
15
Hardware STORE Low to Store Busy
HLBL
Note p: E and G low for output behavior.
Note q: E and G low and W high for output behavior.
Note r: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
25
HLHX
t
HSB (IN)
24
RECOVER
t
22
STORE
t
26
HLBL
t
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA VALID
23
DELAY
t
DQ (DATA OUT)
DATA VALID
March 2006
5
Document Control # ML0008 rev 0.5
CYPRESS [ CYPRESS ]
