STK12C68
e
SRAM READ CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
STK12C68-25
STK12C68-35
STK12C68-45
STK12C68-55
NO.
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
g
25
35
45
55
AVAV
h
3
Address Access Time
25
10
35
15
45
20
55
35
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
h
5
5
5
5
5
5
5
5
5
AXQX
6
ELQX
i
7
10
10
25
10
10
35
12
12
45
12
12
55
EHQZ
HZ
8
0
0
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
i
9
GHQZ
f
f
10
11
ELICCH
EHICCL
PS
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured 200mV from steady state output voltage.
g, h
SRAM READ CYCLE #1: Address Controlled
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
g
SRAM READ CYCLE #2: E Controlled
2
t
AVAV
ADDRESS
1
11
EHICCL
t
ELQV
t
6
E
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
March 2006
3
Document Control # ML0008 rev 0.5
CYPRESS [ CYPRESS ]
