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5962-9311201MXX 参数 Datasheet PDF下载

5962-9311201MXX图片预览
型号: 5962-9311201MXX
PDF下载: 下载PDF文件 查看货源
内容描述: [PLL Based Clock Driver, 7B Series, 2 True Output(s), 0 Inverted Output(s), CMOS, CQCC32, CERAMIC, LCC-32]
分类和应用: 驱动逻辑集成电路
文件页数/大小: 14 页 / 326 K
品牌: CYPRESS [ CYPRESS ]
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CY7B991  
CY7B992  
[2, 13]  
Switching Characteristics Over the Operating Range  
(continued)  
CY7B991–5  
CY7B992–5  
Typ.  
Parameter  
Description  
FS = LOW  
Min.  
15  
Typ.  
Max.  
30  
Min.  
15  
Max.  
30  
Unit  
[1, 2]  
[1, 2]  
f
Operating Clock  
MHz  
NOM  
Frequency in MHz  
FS = MID  
25  
50  
25  
50  
[1, 2 , 3]  
[15]  
FS = HIGH  
40  
80  
40  
80  
t
t
t
t
REF Pulse Width HIGH  
REF Pulse Width LOW  
Programmable Skew Unit  
5.0  
5.0  
5.0  
5.0  
ns  
ns  
RPWH  
RPWL  
U
See Table 1  
Zero Output Matched-Pair Skew  
0.1  
0.25  
0.1  
0.25  
ns  
SKEWPR  
[16, 17]  
(XQ0, XQ1)  
[16, 18]  
t
t
Zero Output Skew (All Outputs)  
0.25  
0.6  
0.5  
0.7  
0.25  
0.6  
0.5  
0.7  
ns  
ns  
SKEW0  
Output Skew (Rise-Rise, Fall-Fall, Same  
SKEW1  
[16, 20]  
Class Outputs)  
t
t
t
Output Skew (Rise-Fall, Nominal-Inverted,  
Divided-Divided)  
0.5  
0.5  
0.5  
1.0  
0.7  
1.0  
0.6  
0.5  
0.6  
1.5  
0.7  
1.7  
ns  
ns  
ns  
SKEW2  
SKEW3  
SKEW4  
[16, 20]  
Output Skew (Rise-Rise, Fall-Fall, Different  
[16, 20]  
Class Outputs)  
Output Skew (Rise-Fall, Nominal-Divided,  
[16, 20]  
Divided-Inverted)  
[14, 21]  
t
t
t
t
t
t
t
t
t
Device-to-Device Skew  
1.25  
+0.5  
+1.0  
2.5  
3
1.25  
+0.5  
+1.2  
4.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ps  
ps  
DEV  
Propagation Delay, REF Rise to FB Rise  
–0.5  
–1.0  
0.0  
0.0  
–0.5  
–1.2  
0.0  
0.0  
PD  
[22]  
Output Duty Cycle Variation  
ODCV  
PWH  
PWL  
ORISE  
OFALL  
LOCK  
JR  
[23, 24]  
Output HIGH Time Deviation from 50%  
[23, 24]  
Output LOW Time Deviation from 50%  
4.0  
[23, 25]  
Output Rise Time  
0.15  
0.15  
1.0  
1.0  
1.5  
1.5  
0.5  
25  
0.5  
0.5  
2.0  
2.0  
3.5  
[23, 25]  
Output Fall Time  
3.5  
[26]  
PLL Lock Time  
0.5  
[14]  
Cycle-to-Cycle Output  
Jitter  
RMS  
25  
[14]  
Peak-to-Peak  
200  
200  
7