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5962-9311201MXX 参数 Datasheet PDF下载

5962-9311201MXX图片预览
型号: 5962-9311201MXX
PDF下载: 下载PDF文件 查看货源
内容描述: [PLL Based Clock Driver, 7B Series, 2 True Output(s), 0 Inverted Output(s), CMOS, CQCC32, CERAMIC, LCC-32]
分类和应用: 驱动逻辑集成电路
文件页数/大小: 14 页 / 326 K
品牌: CYPRESS [ CYPRESS ]
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CY7B991  
CY7B992  
[6]  
Electrical Characteristics Over the Operating Range  
CY7B991  
CY7B992  
Min. Max.  
Parameter  
Description  
Test Conditions  
Min.  
Max.  
Unit  
V
Output HIGH Voltage  
V
V
V
V
= Min., I  
= Min., I  
= 16 mA  
=–40 mA  
2.4  
V
OH  
CC  
CC  
CC  
CC  
OH  
OH  
V
–0.75  
CC  
V
Output LOW Voltage  
= Min., I = 46 mA  
0.45  
V
OL  
OL  
= Min., I = 46 mA  
0.45  
OL  
V
V
V
V
V
Input HIGH Voltage  
(REF and FB inputs only)  
2.0  
V
V
1.35  
V
CC  
V
V
IH  
CC  
CC  
Input LOW Voltage  
(REF and FB inputs only)  
–0.5  
0.8  
–0.5  
1.35  
IL  
Three-Level Input HIGH  
Voltage (Test, FS, xFn)  
Min. V Max.  
V
– 0.85  
V
V
– 0.85  
V
CC  
V
IHH  
IMM  
ILL  
CC  
CC  
CC  
CC  
[7]  
Three-Level Input MID  
Voltage (Test, FS, xFn)  
Min. V Max.  
V
/2 –  
V
/2 +  
V
/2 –  
V /2 +  
CC  
500 mV  
V
CC  
CC  
CC  
500 mV  
CC  
[7]  
500 mV  
500 mV  
Three-Level Input LOW  
Voltage (Test, FS, xFn)  
Min. V Max.  
0.0  
0.85  
0.0  
0.85  
V
CC  
[7]  
I
I
I
I
I
I
I
InputHIGH LeakageCurrent  
(REF and FB inputs only)  
V
V
V
V
V
V
= Max., V = Max.  
10  
10  
µA  
µA  
µA  
µA  
µA  
mA  
mA  
IH  
CC  
CC  
IN  
Input LOW Leakage Current  
(REF and FB inputs only)  
= Max., V = 0.4V  
–500  
–50  
–500  
50  
IL  
IN  
Input HIGH Current  
(Test, FS, xFn)  
= V  
CC  
200  
50  
200  
50  
IHH  
IMM  
ILL  
IN  
Input MID Current  
(Test, FS, xFn)  
= V /2  
IN  
CC  
Input LOW Current  
(Test, FS, xFn)  
= GND  
–200  
–250  
–200  
N/A  
IN  
Output Short Circuit  
= Max., V  
OUT  
OS  
CCQ  
CC  
[8]  
Current  
= GND (25°C only)  
Operating Current Used by  
Internal Circuitry  
V
= V  
=
Com’l  
85  
90  
85  
90  
CCN  
CCQ  
Max., All Input  
Selects Open  
Mil/Ind  
I
Output Buffer Current per  
Output Pair  
V
= V = Max.,  
CCQ  
= 0 mA  
14  
19  
mA  
CCN  
CCN  
[9]  
I
OUT  
Input Selects Open, f  
MAX  
PD  
Power Dissipation per  
Output Pair  
V
= V  
= 0 mA  
= Max.,  
78  
104[11]  
mW  
CCN  
CCQ  
[10]  
I
OUT  
Input Selects Open, f  
MAX  
Notes:  
6. See the last page of this specification for Group A subgroup testing information.  
7. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold  
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time  
before all datasheet limits are achieved.  
8. CY7B991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs  
should not be shorted to GND. Doing so may cause permanent damage.  
9. Total output current per output pair can be approximated by the following expression that includes device current plus load current:  
CY7B991: ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1  
CY7B992: ICCN = [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1  
Where  
F = frequency in MHz  
C = capacitive load in pF  
Z = line impedance in ohms  
N = number of loaded outputs; 0, 1, or 2  
FC = F < C  
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to  
the load circuit:  
CY7B991: PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1  
CY7B992: PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1  
See note 9 for variable definition.  
11. CMOS output buffer current and power dissipation specified at 50-MHz reference frequency.  
4