Application Information: continued
internal circuit. The clamp current is guaranteed to be
can be seen at the VSW pin. Detecting a low output voltage
at the FB pin, the built-in frequency shift feature reduces
the switching frequency to a fraction of its nominal value,
reducing the minimum duty cycle, which is otherwise lim-
ited by the minimum on time of the switch. The peak cur-
rent during this phase is clamped by the internal current
limit.
greater than 1.5A and varies with duty cycle due to slope
compensation. The power switch can withstand a maxi-
mum voltage of 40V on the collector (VSW pin). The satura-
tion voltage of the switch is less than 1V to minimize
power dissipation.
Short Circuit Condition
When the FB pin voltage rises above 0.4V, the frequency
increases to its nominal value, and the peak current begins
to decrease as the output approaches the regulation volt-
age. The overshoot of the output voltage is prevented by
the active pull-on, by which the sink current of the error
amplifier is increased once an overvoltage condition is
detected. The overvoltage condition is defined as when the
FB pin voltage is 50mV greater than the reference voltage.
When a short circuit condition happens in a boost circuit,
the inductor current will increase during the whole switch-
ing cycle, causing excessive current to be drawn from the
input power supply. Since control ICs don’t have the
means to limit load current, an external current limit circuit
(such as fuses and relays) has to be implemented to protect
the load, power supply and ICs.
In other topologies, the frequency shift built into the IC
prevents damage to the chip and external components.
This feature reduces the minimum duty cycle and allows
the transformer secondary to absorb excess energy before
the switch turns back on.
Component Selection
Frequency Compensation
The goal of frequency compensation to achieve desirable
transient response and DC regulation while ensure the sta-
bility of the system. A typical compensation network as
shown in Figure 5 provides a frequency response of two
poles and one zero. This frequency response is further
illustrated in the Bode plot shown in Figure 6.
Startup
I
L
V
V
OUT
CC
VC
R1
CS5171
C2
V
C
C1
Gnd
Figure 5. A typical compensation network.
Figure 4: Startup waveforms of circuit shown in the Application
Diagram. Load = 400mA.
The high DC gain in Figure 6 is desirable for achieving DC
accuracy over line and load variations. The DC gain of a
transconductance error amplifier can be calculated as fol-
lows:
The CS5171 can be activated by either connecting the VCC
pin to a voltage source or by enabling the SS pin. Startup
waveforms shown in Figure 4 are measured in the boost
converter demonstrated in the Application Diagram on the
front cover of this booklet. Recorded after the input voltage
is turned on, this waveform shows the various phases dur-
ing the power up transition.
GainDC = GM × RO
where:
GM = error amplifier transconductance;
RO = error amplifier output resistance ≈ 1MΩ.
When the VCC voltage is below the minimum supply volt-
age, the VSW pin is in high impedance. Therefore, current
conducts directly from the input power source to the out-
put through the inductor and diode. Once VCC reaches
approximately 1.5V, the internal power switch briefly
turns on. This is a part of the CS5171’s normal operation.
The turn-on of the power switch accounts for the initial
current swing.
The low frequency pole fP1 is determined by the error
amplifier output resistance and C1 as :
1
fP1
=
2πC1RO
The first zero is generated by C1 and R1 is:
1
fZ1
=
When the VC pin voltage rises above the threshold, the
internal power switch starts to switch and a voltage pulse
2πC1R1
8
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
