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CS5171GD8 参数 Datasheet PDF下载

CS5171GD8图片预览
型号: CS5171GD8
PDF下载: 下载PDF文件 查看货源
内容描述: [Switching Regulator, Current-mode, 1.5A, 305kHz Switching Freq-Max, PDSO8, 0.150 INCH, SO-8]
分类和应用: 开关光电二极管
文件页数/大小: 16 页 / 189 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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Application Information  
power switch is turned off by the output of the PWM  
Theory of Operation  
Current Mode Control  
Comparator.  
A TTL-compatible sync input at the SS pin is capable of  
syncing up to 1.8 times the base oscillator frequency. As  
shown in Figure 2, in order to sync to a higher frequency, a  
positive transition turns on the power switch before the  
output of the oscillator goes high thereby resetting the  
oscillator. The sync operation allows multiple power sup-  
plies to operate at the same frequency.  
VCC  
Oscillator  
S
R
Q
L
VC  
-
+
D1  
Power Switch  
In  
PWM LATCH  
VSW  
PWM Comparator  
A sustained logic low at the SS pin will shut down the IC  
and reduce the supply current.  
Out  
Driver  
C0  
RLOAD  
X5  
An additional feature includes frequency shift to 20% of  
the nominal frequency when the FB pin triggers the thresh-  
old. During power up, overload, or short circuit condi-  
tions, the minimum switch on time is limited by the PWM  
comparator blanking period. Extra switch off time reduces  
the minimum duty cycle to protect external components  
and the IC itself.  
63mΩ  
Slope Compensation  
Figure 1. Current Mode Control Scheme  
The CS5171 incorporates a current mode control scheme, in  
which the PWM ramp signal is derived from power switch  
current. This ramp signal is compared to the output of the  
error amplifier to control the on time of the power switch.  
The oscillator is used as a fixed frequency clock to ensure a  
constant operational frequency. The resulting control  
scheme features several advantages over the conventional  
voltage mode controller. First, derived directly from the  
inductor, the ramp signal responds immediately to line  
voltage changes. This eliminates the delay caused by the  
output filter and error amplifier, which is commonly suf-  
fered in voltage mode controllers. The second benefit  
comes from inherent pulse-by-pulse current limiting by  
merely clamping the peak switching current. Finally, since  
current mode commands an output current rather than  
voltage, the filter offers only a single pole to the feedback  
loop. This allows both simpler compensation and a higher  
gain bandwidth over a comparable voltage mode circuit.  
As previously mentioned, this block also produces a ramp  
for the slope compensation to improve regulator stability.  
Error Amplifier  
+
-
1.276V  
V
C
C1  
0.01µF  
FB  
1MΩ  
Voltage  
Clamp  
120pF  
positive error-amp  
CS5171  
R1  
5kΩ  
Figure 3. Error amplifier equivalent circuit.  
Without discrediting its apparent merits, current mode  
control comes with its own peculiar problems, mainly, sub-  
harmonic oscillation at duty cycle over 50%. The CS5171  
solves this problem by adopting a slope compensation  
scheme in which a fixed ramp generated by the oscillator is  
added to the current ramp. A proper slope rate is provided  
to improve circuit stability without sacrificing the advan-  
tages of current mode control.  
The FB pin is directly connected to the inverting input of  
the positive error amplifier, whose non–inverting input is  
fed by the 1.276V reference. Both amplifiers are transcon-  
ductance amplifiers with a high output impedance of  
approximately 1Mas shown in Figure 3. The VC pin is  
connected to the output of the error amplifiers and is inter-  
nally clamped between 0.5V and 1.7V. A typical connec-  
tion at the VC pin includes a capacitor in series with a resis-  
tor to ground, forming a pole/zero for loop compensation.  
Oscillator and Shutdown  
An external shunt can be connected between the VC pin  
and ground to reduce its clamp voltage. Consequently, the  
current limit of the internal power transistor current is  
reduced from its nominal value.  
Sync  
Current Ramp  
V
SW  
Switch Driver and Power Switch  
The switch driver receives a control signal from the logic  
section to drive the output power switch. The switch is  
grounded through emitter resistors (63mtotal) to the  
PGnd pin. PGnd is not connected to the IC substrate so  
that switching noise can be isolated from the analog  
ground. The peak switching current is clamped by an  
Figure 2. Timing Diagram of Sync and Shut Down.  
The oscillator is trimmed to guarantee an 13% frequency  
accuracy. As shown in Figure 1, the output of the oscillator  
turns on the power switch at a frequency of 270kHz. The  
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