Application Information: continued
Typical Performance Characteristics
The VREF (ok) comparator monitors the 3.3V VREF output
and latches a fault condition if VREF falls below 3.1V. The
fault condition may also be triggered when the OV pin
voltage rises above 2V or the UV pin voltage falls below
1V. The under-voltage comparator has a built-in hysteresis
of 75mV (typ). The hysteresis for the OV comparator is
programmable through a resistor connected to the OV pin.
When an OV condition is detected, the over-voltage hys-
teresis current of 12.5µA (typ) is sourced from the pin.
In Fig.4, the fault condition is triggered by pulling the UV
pin to the ground. Immediately, the SS capacitor is dis-
charged with 5µA of current (typ) and the GATE output is
disabled until the SS voltage reaches the discharge voltage
of 0.3V (typ). The IC starts the Soft Start transition again if
the fault condition has recovered as shown in Fig.4.
However, if the fault condition persists, the SS voltage will
stay at 0.10V until the removal of the fault condition.
Figure 5: The GATE output is terminated when the ISENSE pin voltage
reaches the threshold set by the ISET pin. CH2: ISENSE pin, CH4: ISETpin,
CH3: GATE pin
The current sense signal is prone to leading edge spikes
caused by the switching transition. A RC low-pass filter is
usually applied to the current signals to avoid premature
triggering. However, the low pass filter will inevitably
change the shape of the current pulse and also add cost.
The CS51221uses leading edge blanking circuitry that
blocks out the first 150ns (typ) of each current pulse. This
removes the leading edge spikes without altering the cur-
rent waveform. The blanking is disabled during Soft Start
and when the VCOMP is saturated high so that the mini-
mum on-time of the controller does not have the additional
blanking period. The max SS detect comparator keeps the
blanking function disabled until SS charges fully. The out-
put of the max Duty Cycle detector goes high when the
error amplifier output gets saturated high, indicating that
the output voltage has fallen well below its regulation
point and the power supply may be under load stress.
Figure 4: The fault condition is triggered when the UV pin voltage falls
below 1V. The Soft Start capacitor is discharged and the GATE output
is disabled. CH2: Envelop of GATE output, CH3: SS pin with 0.01µF
capacitor, CH4: UV pin.
Oscillator and Synchronization
Current Sense and Over Current Protection
The switching frequency is programmable through a RC
network connected to the RTCT Pin. As shown in Fig.6,
when the RTCT pin reaches 2V, the capacitor is discharged
by a 1mA current source and the Gate signal is disabled.
When the RTCT pin decreases to 1V, the Gate output is
turned on and the discharge current is removed to let the
RTCT pin ramp up. This begins a new switching cycle. The
CT charging time over the switch period sets the maximum
duty cycle clamp which is programmable through the RT
value as shown in the Design Guidelines. At the beginning
of each switching cycle, the SYNC pin generates a 2.5V,
320nS (typ) pulse. This pulse can be utilized to synchronize
other power supplies.
The current can be monitored by the ISENSE pin to achieve
pulse by pulse current limit. Various techniques, such as a
using current sense resistor or current transformer, can be
adopted to derive current signals. The voltage of the ISET
pin sets the threshold for maximum current. As shown in
Fig. 5, when the ISENSE pin voltage exceeds the ISET voltage,
the current limit comparator will reset the GATE latch flip-
flop to terminate the GATE pulse.
8
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
