Package Pin Description
Typical Performance Characteristics
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16L PDIP & 16L SO Narrow
1
GATE
External power switch driver with 1.0A peak capability. Rail to
rail output occurs when the capacitive load is between 470pF
and 10nF.
2
3
4
5
6
7
ISENSE
SYNC
FF
Current sense comparator input.
Bidirectional synchronization. Locks to highest frequency.
PWM ramp.
UV
Undervoltage protection monitor.
OV
Overvoltage protection monitor.
RT/CT
Timing resistor RT and capacitor CT determine oscillator
frequency and maximum duty cycle, DMAX
.
8
9
ISET
VFB
Voltage at this pin sets pulse-by-pulse overcurrent threshold.
Feedback voltage input. Connected to the error amplifier
inverting input.
10
11
COMP
SS
Error amplifier output.
Charging external capacitor restricts error amplifier output
voltage during the power up or fault conditions.
Logic Ground.
12
13
LGnd
VREF
3.3V reference voltage output. Decoupling capacitor can be
selected from 0.01µF to 10µF.
14
15
16
VCC
PGnd
VC
Logic supply voltage.
Output power stage ground.
Output power stage supply voltage.
Block Diagram
VCC
VREF
3.3V
2mA(maximum load current)
UVL
Thermal
Shutdown
V
= 3.3V
VREF OK
REF
ENABLE
+
-
3.1V
VC
Low
UV Lockout
Start/Stop
Sat
Gate
Driver
S
R
Q
G
1
GATE
SYNC
RTCT
OSC
13.5V
G2
Q
2V to 1V Trip Points
PGnd
LGnd
3.0V
Max Duty Cycle
(Sat Sense)
VBG
(1.263V)
EAMP
SS to 1.8V Max
VREF
VFB
50µA
COMP
PWM
Comp
Soft Start Clamp
FF
ON
FF Discharge
VO Off
Latching
Discharge
G
SS
OV
4
G3
5µA
Max SS
Det
OV Monitor
ISET
3.0V
2V
ILIM
DISABLE
150ns
Blank
(Sat Sense)
UV
UV Monitor
ISENSE
1V
6
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
