50S116T
SDRAM
6. BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CS
CONTROL
COLUMN DECODER
SIGNAL
RAS
CAS
WE
GENERATOR
R
O
COMMAND
DECODER
W
CELL ARRAY
BANK #0
D
E
C
O
D
E
R
SENSE AMPLIFIER
A10
A0
MODE
REGISTER
ADDRESS
BUFFER
A9
BA
DQ0
DQ
DATA CONTROL
CIRCUIT
BUFFER
DQ15
LDQM
UDQM
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
R
O
W
CELL ARRAY
BANK #1
D
E
C
O
D
E
R
SENSE AMPLIFIER
Note: The cell array configuration is 2048 * 256 * 16
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Aug.20,2002
Page 6 of 42
Fax:886-3-3521052
CERAMATE [ CERAMATE TECHNICAL ]
