50S116T
SDRAM
5. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
Address
Multiplexed pins for row and column address.
20 - 24,
27 - 32
A0 - A10
Row address: A0- A10. Column address: A0 - A7.
19
BA
Bank Select Select bank to activate during row address latch time,
or bank to read/write during column address latch time.
2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
42, 43, 45, 46,
48, 49
Data Input/
Output
DQ0 - DQ15
Multiplexed pins for data input and output.
18
Chip Select Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
CS
17
Row Address Command input. When sampled at the rising edge of
RAS
Strobe
the clock, RAS, CAS and WE define the
operation to be executed.
16
Column
Address
Strobe
CAS
WE
Referred to RAS
Referred to RAS
15
Write Enable
36, 14
UDQM/
LDQM
Input/Output The output buffer is placed at Hi-Z (with latency of 2)
Mask
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
with zero latency.
35
34
CLK
CKE
Clock Inputs System clock used to sample inputs on the rising edge
of clock.
Clock Enable CKE controls the clock activation and deactivation.
When CKE is low, Power-down mode, Suspend mode,
or Self Refresh mode is entered.
1, 25
VCC
Power
Power for input buffers and logic circuit inside DRAM.
(+3.3V)
26, 50
VSS
Ground
Power
Ground for input buffers and logic circuit inside DRAM.
Separated power from VCC, used for output buffers to
7, 13, 38, 44,
VCCQ
(+3.3V) for improve noise immunity.
I/O buffer
4, 10, 41, 47
33, 37
VSSQ
NC
Ground for Separated ground from VSS, used for output buffers to
I/O buffer improve noise immunity.
No
No connection
Connection
* All specs and applications shown above subject to change without prior notice.
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Rev 1.0 Aug.20,2002
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