CAT28LV64
(4)
Figure 1. A.C. Testing Input/Output Waveform
V
- 0.3 V
CC
2.0 V
0.6 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.0 V
Figure 2. A.C. Testing Load Circuit (example)
Vcc
1.8 K
DEVICE
UNDER
TEST
OUTPUT
1. 3K
C = 100 pF
L
C INCLUDES JIG CAPACITANCE
L
A.C. CHARACTERISTICS, Write Cycle
= 3.0V to 3.6V, unless otherwise specified.
V
cc
28LV64-15
Min Max
28LV64-20
Min Max
28LV64-25
Symbol
Parameter
Min
Max
Units
ms
ns
tWC
tAS
tAH
tCS
tCH
Write Cycle Time
Address Setup Time0
Address Hold Time
CE Setup Time
CE Hold Time
5
5
5
0
100
0
0
100
0
0
100
0
ns
ns
0
0
0
ns
(2)
tCW
tOES
tOEH
CE Pulse Time
OE Setup Time
OE Hold Time
110
0
150
10
10
150
100
0
150
10
10
150
100
0
ns
ns
0
ns
(2)
tWP
tDS
tDH
WE Pulse Width
Data Setup Time
Data Hold Time
110
60
0
ns
ns
ns
(1)
tINIT
Write Inhibit Period
After Power-up
5
10
5
10
5
10
ms
(1)(3)
tBLC
Byte Load Cycle Time
0.05
100
0.1
100
0.1
100
µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration t
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
BLC
however a transition from HIGH to LOW within t
max. stops the timer.
BLC
(4) Input rise and fall times (10% and 90%) < 10 ns.
Doc. No. 1010, Rev. D
5
CATALYST [ CATALYST SEMICONDUCTOR ]
