CAT28LV64
64K-Bit CMOS PARALLEL EEPROM
FEATURES
■
3.0V to 3.6 V Supply
■
Read access times:
■
CMOS and TTL compatible I/O
■
Automatic page write operation:
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
– 150/200/250ns
■
Low power CMOS dissipation:
– 1 to 32 bytes in 5ms
– Page load timer
■
End of write detection:
– Active: 8 mA max.
– Standby: 100
µ
A max.
■
Simple write operation:
– Toggle bit
–
DATA
polling
■
Hardware and software write protection
■
100,000 program/erase cycles
■
100 year data retention
– On-chip address and data latches
– Self-timed write cycle with auto-clear
■
Fast write cycle time:
– 5ms max.
■
Commercial, industrial and automotive
temperature ranges
DESCRIPTION
The CAT28LV64 is a low voltage, low power, CMOS
parallel EEPROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and V
CC
power up/down write protection eliminate
additional timing and protection hardware.
DATA
Polling
and Toggle status bit signal the start and end of the self-
timed write cycle. Additionally, the CAT28LV64 features
hardware and software write protection.
The CAT28LV64 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
BLOCK DIAGRAM
A5–A12
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
8,192 x 8
E
2
PROM
ARRAY
32 BYTE PAGE
REGISTER
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
I/O0–I/O7
A0–A4
ADDR. BUFFER
& LATCHES
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1010, Rev. D
CATALYST [ CATALYST SEMICONDUCTOR ]
