BSI
BS616LV2025
AC TEST CONDITIONS
KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Vcc/0V
1V/ns
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
AC TEST LOADS AND WAVEFORMS
Ω
Ω
1928
1928
5PF
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
5.0V
5.0V
OUTPUT
OUTPUT
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
100PF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
ANY CHANGE
PERMITTED
Ω
Ω
1020
1020
DOES NOT
APPLY
CENTER
FIGURE 1A
THEVENIN EQUIVALENT
FIGURE 1B
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns CYCLE TIME : 55ns
MIN. TYP. MAX. MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
UNIT
tAVAX
tAVQV
tE1LQV
tE2LQV
tBA
tRC
70
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
55
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
70
70
70
35
35
--
55
55
55
30
30
--
tACS1
tACS2
tBA
(CE1)
(CE2)
Chip Select Access Time
--
--
--
--
--
--
--
--
--
--
--
--
--
Chip Select Access Time
--
--
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
(LB,UB)
--
--
tGLQV
tELQX
tBE
tOE
--
--
tCLZ
tBE
(CE1,CE2) 10
(LB,UB) 10
10
10
10
10
--
--
--
tGLQX
tEHQZ
tBDO
tOLZ
tCHZ
tBDO
tOHZ
tOH
--
--
Chip Deselect to Output in High Z (CE1,CE2)
--
--
35
35
30
--
30
30
25
--
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
(LB, UB)
--
tGHQZ
tAXOX
--
--
10
10
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
Revision 2.5
Jan. 2004
R0201-BS616LV2025
6